公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO2005043590A3

公开(公告)日：2006-09-21

申请号：PCT/US2004034528

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括用于pFET（40）和nFET（45）的沟道。 在nFET沟道的沟道中生长SiGe层（45a），并且在pFET沟道中生长Si：C层（40a）。 SiGe和Si：C匹配下层Si层（15）的晶格网络，以在上覆的生长的外延层（60）中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在进一步的实施中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：JP2007300103A

公开(公告)日：2007-11-15

申请号：JP2007113990

申请日：2007-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MOCUTA ANDA C ,  CHIDAMBARRAO DURESETI ,  DONATON RICARDO A ,  KERN RIM ,  ONSONGO DAVID MASARA

IPC: H01L21/20 ,  H01L21/338 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To reduce the formation of misfit dislocation that may reduce the charge mobility and device performance. SOLUTION: There is provided a method of manufacturing a semiconductor structure and a semiconductor device, more specifically, an N-type FET device. The device includes a stress receiving layer provided on a stress inducing layer via a material at an interface between the layers, which reduces the occurrence and propagation of misfit dislocation in the structure. The stress receiving layer includes silicon (Si), the stress inducing layer includes silicon-germanium (SiGe), and the material includes carbon given by doping both layers during the period of the formation of the device. The carbon can be doped over the entire SiGe layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：减少可能降低电荷迁移率和器件性能的失配位错的形成。 解决方案：提供一种制造半导体结构和半导体器件的方法，更具体地说，涉及一种N型FET器件。 该装置包括通过层之间的界面处的材料在应力诱导层上提供的应力接收层，这减少了结构中失配位错的发生和传播。 应力接收层包括硅（Si），应力诱导层包括硅锗（SiGe），并且该材料包括在器件形成期间通过掺杂两层给出的碳。 碳可以掺杂在整个SiGe层上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007294950A

公开(公告)日：2007-11-08

申请号：JP2007103478

申请日：2007-04-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  JOHN JOSEF ELLIS-MONAHAN ,  GREENE BRIAN J

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/823814

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a transistor device with a dopant depth which is extended and increased so as to have no effect on a channel region of a transistor.
SOLUTION: The method comprises: (a) a step of providing a substrate comprising a semiconductor-on-insulator structure ("SOI") layer separated from a bulk region in the substrate by an embedded dielectric layer; (b) a step of performing a first implantation to the SOI layer in order to attain a predetermined concentration of dopant in an interface of the SOI layer to the embedded dielectric layer; and (c) a step of performing a second implantation to the SOI layer in order to attain a predetermined concentration of dopant in a polycrystalline semiconductor gate conductor ("poly gate") as well as in a source region and a drain region which are arranged to be adjacent to the poly gate. The maximum depth of the first implantation is deeper than the maximum depth of the second implantation.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成具有扩展和增加的掺杂剂深度的晶体管器件的方法，以便对晶体管的沟道区域没有影响。 解决方案：该方法包括：（a）提供包括绝缘体上半导体结构（“SOI”）层的衬底的步骤，该衬底通过嵌入的电介质层与衬底中的本体区域分离; （b）为了在SOI层与嵌入介电层的界面中获得预定浓度的掺杂剂，对SOI层进行第一次注入的步骤; 以及（c）为了在多晶半导体栅极导体（“多晶硅”）以及源极区和漏极区中排列的多个半导体栅极导体（“多晶硅”）以及源极区和漏极区域中的掺杂剂浓度达到预定浓度，对SOI层进行第二注入的步骤 与多门相邻。 第一植入的最大深度比第二植入的最大深度更深。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007158323A

公开(公告)日：2007-06-21

申请号：JP2006311038

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  KERN RIM ,  GREENE BRIAN J

IPC: H01L29/786 ,  H01L21/76 ,  H01L29/78

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a stress-producing dielectric element which underlies the entire undersurface of an active semiconductor region.
SOLUTION: A compressive stress is applied to a channel region of a PFET by a structure including an independent stress-producing dielectric element that entirely underlies the bottom surface of an active semiconductor region in which a source, a drain and a channel region of the PFET are disposed. Specifically, the stress-producing dielectric element includes a region of a collapsed oxide which contacts the entire bottom surface of the active semiconductor region so that it has an area of the same spread as an area of the bottom surface. Bird beak-like oxide regions at the edges of the stress-producing dielectric element apply an upward force to the edges of the stress-producing dielectric element to provide a compressive stress to the channel region of the PFET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有产生应力的介电元件的晶体管，其在有源半导体区域的整个下表面的下方。 解决方案：通过包括独立的产生应力的电介质元件的结构将压应力施加到PFET的沟道区域，该电介质元件完全位于有源半导体区域的底表面之下，其中源极，漏极和沟道区域 的PFET。 具体而言，应力产生用电介质元件包括与活性半导体区域的整个底面接触的塌陷氧化物的区域，使得其具有与底面的面积相同的面积。 产生应力的电介质元件边缘处的鸟形喙状氧化物区向产生应力的电介质元件的边缘施加向上的力，以向PFET的沟道区提供压缩应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005175480A

公开(公告)日：2005-06-30

申请号：JP2004353535

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN C ,  CHIDAMBARRAO DURESETI ,  LI YUJUN ,  SETTLEMYER KENNETH T JR

IPC: H01L21/308 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a FinFET which allows an integrated circuit or an electronic device that includes smaller, more densely disposed active regions or active lines.
SOLUTION: A method of forming an integrated circuit having a FinFET comprises a method of forming sub-lithographic fins. A silicon block is defined by a mask, and a pair of fins which is reduced in width or pulled back by the thickness of one fin on each side is included. After that, a second mask is formed around the first mask so that an aperture having the width of the separation distance between the pair of fins remains in the second mask after the first mask is removed. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining the fin thickness by the pullback step.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种FinFET，其允许集成电路或包括更小，更密集布置的有源区或有源线的电子器件。 解决方案：一种形成具有FinFET的集成电路的方法包括形成亚光刻鳍片的方法。 硅块由掩模限定，并且包括在每侧具有一个翅片的宽度减小或拉回的一对翅片。 之后，在第一掩模周围形成第二掩模，使得在去除第一掩模之后，具有一对散热片之间的间隔距离的宽度的孔保持在第二掩模中。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过回拉步骤限定翅片厚度。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004111957A

公开(公告)日：2004-04-08

申请号：JP2003310635

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEGDE SURYANARAYAN G ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure and the method of forming an integrated circuit including a low programming voltage anti-fuse on a semiconductor substrate. SOLUTION: This integrated circuit is formed by doping a part of a semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric that is destroyed by the application of breakdown voltage on the doped portion of the semiconductor substrate, forming a first conductor that is separated from the semiconductor substrate by the thin dielectric, and forming a second conductor that is conductively connected with the doped portion of the semiconductor substrate. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：WO2007025259A2

公开(公告)日：2007-03-01

申请号：PCT/US2006033582

申请日：2006-08-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

Inventor： CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

IPC: H01L29/00

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/165

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having abase region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 ran thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract translation: 本发明涉及一种具有其中含SiGe的层的碱性区的高性能异质结双极晶体管（HBT）。 含SiGe的层的厚度不超过约100埃，具有预定的临界锗含量。 含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量本发明还涉及通过均匀增加的具有含SiGe的基底层来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法 基底层中的锗含量，使得其中的平均锗含量不小于基于基底层的厚度计算的临界锗含量的80％，条件是基底层不大于100nm厚。

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。