公开(公告)号：US3449728A

公开(公告)日：1969-06-10

申请号：US3449728D

申请日：1966-01-28

Applicant: IBM

Inventor： HENLE ROBERT A ,  PRICER WILBUR D

IPC: G11C11/411 ,  G11C19/28 ,  H03K3/037 ,  H03K3/286 ,  H03K3/2893 ,  H03K3/26

CPC classification number: G11C11/411 ,  G11C19/28 ,  H03K3/037 ,  H03K3/286 ,  H03K3/2893

公开(公告)号：US3089964A

公开(公告)日：1963-05-14

申请号：US81517459

申请日：1959-05-22

Applicant: IBM

Inventor： BRUCE GEORGE D ,  HENLE ROBERT A

IPC: H03K19/082

CPC classification number: H03K19/082

公开(公告)号：US3031584A

公开(公告)日：1962-04-24

申请号：US51862055

申请日：1955-06-28

Applicant: IBM

Inventor： HENLE ROBERT A

IPC: H03K19/082

CPC classification number: H03K19/082

公开(公告)号：US2971696A

公开(公告)日：1961-02-14

申请号：US41269754

申请日：1954-02-26

Applicant: IBM

Inventor： HENLE ROBERT A

IPC: G06F7/50 ,  G06F7/502

CPC classification number: G06F7/502 ,  G06F7/5013 ,  G06F2207/4818

公开(公告)号：US2963594A

公开(公告)日：1960-12-06

申请号：US78767859

申请日：1959-01-19

Applicant: IBM

Inventor： BRUCE GEORGE D ,  HENLE ROBERT A ,  WALSH JAMES L

IPC: H03K19/082

CPC classification number: H03K19/082

公开(公告)号：US2943791A

公开(公告)日：1960-07-05

申请号：US47809454

申请日：1954-12-28

Applicant: IBM

Inventor： HENLE ROBERT A ,  WOOD MARION L

IPC: G06F7/38 ,  H03K19/082 ,  H03K19/16

CPC classification number: H03K19/16 ,  G06F7/383 ,  H03K19/082

公开(公告)号：US2861200A

公开(公告)日：1958-11-18

申请号：US45938154

申请日：1954-09-30

Applicant: IBM

Inventor： HENLE ROBERT A ,  EMERY RAYMOND W ,  BRUCE GEORGE D ,  MAC SORLEY OLIN L

IPC: H03K3/012 ,  H03K3/286 ,  H03K3/288

CPC classification number: H03K3/288 ,  H03K3/012 ,  H03K3/286

公开(公告)号：CA612596A

公开(公告)日：1961-01-17

申请号：CA612596D

Applicant: IBM

Inventor： HENLE ROBERT A

公开(公告)号：FR2337464A1

公开(公告)日：1977-07-29

申请号：FR7636402

申请日：1976-11-29

Applicant: IBM

Inventor： HENLE ROBERT A ,  HO IRVING T

IPC: H03F3/345 ,  H03F3/34 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944 ,  G11C5/00

Abstract: An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS CP = 2ROOT C(P-1) . C(P+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

公开(公告)号：CA716714A

公开(公告)日：1965-08-24

申请号：CA716714D

Applicant: IBM

Inventor： DOMENICO ROBERT J ,  HENLE ROBERT A