公开(公告)号：JP2005311366A

公开(公告)日：2005-11-04

申请号：JP2005119003

申请日：2005-04-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  CHIRAS STEFANIE R ,  DALTON TIMOTHY ,  DEMAREST JAMES J ,  DUNN DERREN N ,  DZIOBKOWSKI CHESTER T ,  FLAITZ PHILIP L ,  LANE MICHAEL W ,  LLOYD JAMES R ,  DARYL D RESUTAINO ,  SHAW THOMAS M ,  WANG YUN YU ,  YANG CHIH-CHAO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To realize an interconnection structure that improves the adhesion between an upper low-k dielectric layer and a diffusion barrier cap dielectric layer existing therebeneath. SOLUTION: In the interconnection structure, adhesion between the upper low-k (for example, the dielectric coefficient is less than 4.0) dielectric layer (for example, a dielectric containing an element group consisting of Si, C, O, and H) and the diffusion barrier cap dielectric layer (for example, a cap layer containing an element group consisting of C, Si, N, and H) existing therebeneath is improved, by providing an adhesion transition layer in between the two layers. Because the adhesion transition layer exists between the upper low-k dielectric layer and the diffusion barrier cap dielectric layer, the possibility that the layers in the interconnection structure are separated in a packaging process is reduced. The adhesion transition layer provided here comprises a lower SiO x (or SiON) contained region and an upper C inclination region. Such a structure and, in particular, a method for forming an adhesion transition layer are also provided. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现改善上部低k电介质层和存在于其之间的扩散阻挡盖电介质层之间的粘附性的互连结构。 解决方案：在互连结构中，上部低k（例如，介电系数小于4.0）电介质层（例如，包含由Si，C，O和 H）和扩散阻挡盖电介质层（例如，包含由C，Si，N和H构成的元素组的覆盖层）提高，通过在两层之间提供粘合过渡层。 由于粘附过渡层存在于上部低k电介质层和扩散阻挡层电介质层之间，因此在封装过程中互连结构中的层分离的可能性降低。 这里提供的粘合过渡层包含较低的SiO xS（或SiON）含有区域和上C倾斜区域。 还提供了这种结构，特别是形成粘附过渡层的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004336051A

公开(公告)日：2004-11-25

申请号：JP2004136335

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2008205458A

公开(公告)日：2008-09-04

申请号：JP2008028398

申请日：2008-02-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  CHANDA KAUSHIK ,  WANG PING-CHUAN

IPC: H01L21/3205 ,  H01L23/52

CPC classification number: H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method of fabricating an interconnect structure with a bi-layer metal cap. SOLUTION: In one embodiment, this method of fabricating an interconnect structure with a bi-layer metal cap includes the steps of: forming an interconnect structure portion in a dielectric material layer; and forming a bi-layer metallic cap on the top surface of an interconnect structure portion. This method also includes the step of depositing the blanket layer of a dielectric capping layer, which covers the exposed surface of the dielectric material layer and the surface of a bi-layer metallic cap. The bi-layer metallic cap comprises: a metal capping layer formed on the conductive surface of an interconnect structure portion; and metal nitride formed on the top portion of the metal capping layer. The interconnect structure comprises: an interconnect structure portion formed in the dielectric layer: a bi-layer metallic cap formed on the top portion of the interconnect structure portion; and a dielectric capping layer formed on the bi-layer metallic cap. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用双层金属帽制造互连结构的结构和方法。 解决方案：在一个实施例中，制造具有双层金属帽的互连结构的这种方法包括以下步骤：在介电材料层中形成互连结构部分; 以及在互连结构部分的顶表面上形成双层金属帽。 该方法还包括沉积介电覆盖层的覆盖层的步骤，该覆盖层覆盖介电材料层的暴露表面和双层金属盖的表面。 双层金属盖包括：形成在互连结构部分的导电表面上的金属覆盖层; 和金属氮化物形成在金属覆盖层的顶部上。 所述互连结构包括：形成在所述电介质层中的互连结构部分：形成在所述互连结构部分的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007251164A

公开(公告)日：2007-09-27

申请号：JP2007058015

申请日：2007-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  KLYMKO NANCY R ,  KEITH KWONG HON WONG ,  CHRISTOPHER C PARKS

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure of a single or dual/damascene type which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer, and a method of forming the same.
SOLUTION: According to this structure, a hydrogen plasma treatment is used in order to treat the noble metal seed layer, so that the treated noble metal seed layer is very highly resistant to surface oxidation. This oxidation-resistant noble metal seed layer has a low C content or a low nitrogen content, or the both.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种单/双/镶嵌型的互连结构，其基本上减少了将导电材料电镀到贵金属种子层上的表面氧化问题及其形成方法。 解决方案：根据该结构，为了处理贵金属种子层，使用氢等离子体处理，使得处理的贵金属种子层对表面氧化非常高。 这种抗氧化贵金属种子层具有低C含量或低氮含量，或两者。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007227921A

公开(公告)日：2007-09-06

申请号：JP2007037720

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/316

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31633 ,  H01L21/7682 ,  H01L21/76831

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric having a reduced dielectric constant, and to provide its manufacturing method.
SOLUTION: In a first embodiment, a first method of manufacturing a dielectric having a reduced dielectric constant is provided. The first method includes the steps of: (1) forming a dielectric layer including a trench on a substrate; and (2) forming a cladding region in the dielectric layer by forming a plurality of air gaps in the dielectric layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric. Numerous other aspects are provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有降低的介电常数的电介质，并提供其制造方法。 解决方案：在第一实施例中，提供了制造具有降低的介电常数的电介质的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个在电介质层中形成多个空气间隙来形成电介质层中的包层区域，以便降低电介质的有效介电常数。 提供了许多其他方面。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004158851A

公开(公告)日：2004-06-03

申请号：JP2003359944

申请日：2003-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LARRY ,  KLEPEIS STANLEY ,  LU HSIAO-LING ,  MARINO JEFFREY ,  SIMON ANDREW HERBERT ,  WANG YUN-YU ,  WONG KWONG HON ,  YANG CHIH-CHAO

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To solve the problem of carbon contamination that dos not occur in circuits using oxide as dielectric, which exists in advanced technology using low-k organic-based interlayer dielectrics in copper backend integrated circuit technology. SOLUTION: A composite liner layer for the copper lines uses Ti as a bottom layer, which has property of gettering carbon and other contaminants. The known problem of Ti as reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2011014904A

公开(公告)日：2011-01-20

申请号：JP2010142938

申请日：2010-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  THEODORUS EDUARDUS STANDAERT ,  EDELSTEIN DANIEL C

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure including a gouging feature at the bottom of a via opening, and to provide a method of fabricating the same.SOLUTION: The method does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature.

Abstract translation: 要解决的问题：提供一种在通孔开口的底部包括刨花特征的互连结构，并提供其制造方法。解决方案：该方法不会破坏线中沉积的沟槽扩散阻挡层的覆盖 位于通孔开口顶部的开口，和/或不引入由通过溅射在通孔开口的底部通过包括通孔和线路开口的互连电介质材料产生气流特征而造成的损害。 通过在互连电介质中首先形成线路开口，然后形成通孔开口，然后形成沟槽特征，在通孔开口的底部提供气泡特征来实现这种互连结构。

公开(公告)号：JP2010283347A

公开(公告)日：2010-12-16

申请号：JP2010123865

申请日：2010-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOGAMI TAKESHI ,  EDELSTEIN DANIEL C ,  ROSSNAGEL STEPHEN M ,  FLAITZ PHILIP LEE ,  DEHAVEN PATRICK WILLIAM ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/52

CPC classification number: H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of attaining high reliability and a high production yield by eliminating a void generation portion in a liner/copper interface. SOLUTION: The method of forming a diffusion barrier used for manufacturing the semiconductor device includes a step for depositing an iridium-doped tantalum-based barrier layer on a pattern-formed intermediate dielectric (ILD) layer by a physical vapor deposition (PVD) process, and the barrier layer is deposited to form the barrier layer into amorphous structure as a result, at least 60% of an iridium concentration in terms of atomic weight. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过消除衬里/铜界面中的空隙生成部分来制造能够获得高可靠性和高生产率的半导体器件的方法。 解决方案：形成用于制造半导体器件的扩散阻挡层的方法包括通过物理气相沉积（PVD）在形成图案的中间电介质（ILD）层上沉积铱掺杂的钽基阻挡层的步骤 ），并且阻挡层被沉积以形成无定形结构的阻挡层，至少60％的铱浓度以原子量计。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007300113A

公开(公告)日：2007-11-15

申请号：JP2007118453

申请日：2007-04-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  CHANDA KAUSHIK

IPC: H01L21/3205 ,  C23C14/34 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/76844 ,  C23C14/046 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76846

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection structure having a barrier material coverage range in which the barrier material thickness of the sidewall of the structure is larger than that of the bottom portion of the structure, and to provide the method of manufacturing such interconnection structure.
SOLUTION: There are provided an interconnection structure having a barrier material coverage range in which the barrier material thickness of the sidewall of the structure is larger than that of the bottom portion of the structure, and the method of manufacturing such interconnection structure. The interconnection structure of the invention has improved technical extensibility for semiconductor society compared with the interconnection structure of the prior art in which a barrier material is formed by a conventional PVD process, conventional ionized plasma deposition, CVD, or ALD. According to the invention, there is provided the interconnection structure having the barrier material thickness (w
t ) of the sidewall of the structure larger than the barrier material thickness (h
t ) of the bottom portion of the structure. That is, in the interconnection structure of the invention, w
t /h
t fraction is equal to or more than 100%.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有屏障材料覆盖范围的互连结构，其中结构的侧壁的阻挡材料厚度大于结构的底部的阻挡材料厚度，并且提供制造方法 这样的互连结构。 解决方案：提供了一种具有阻挡材料覆盖范围的互连结构，其中该结构的侧壁的阻挡材料厚度大于该结构的底部的阻挡材料厚度，以及制造这种互连结构的方法。 与现有技术的互连结构相比，本发明的互连结构提高了技术可扩展性，其中通过常规PVD工艺，常规电离等离子体沉积，CVD或ALD形成阻挡材料。 根据本发明，提供了具有大于阻挡材料厚度（h t ）的结构的侧壁的阻挡材料厚度（w t ）的互连结构， 的结构的底部。 也就是说，在本发明的互连结构中，w / h t 分数等于或大于100％。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007243187A

公开(公告)日：2007-09-20

申请号：JP2007052225

申请日：2007-03-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEITH KWONG HON WONG ,  WILDMAN HORATIO S ,  YANG CHIH-CHAO ,  WANG YUN YU ,  CHRISTOPHER C PARKS

IPC: H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide new MOL metallurgy for avoiding a defect by using the MOL metallurgy of a prior art and its manufacturing method. SOLUTION: There is provided a semiconductor structure comprising a Co-containing liner arranged between an oxygen getter layer and a conductive material containing metal. The Co-containing liner, the oxygen getter layer, and the conductive material containing the metal form MOL metallurgy in which the Co-containing liner substitutes a conventional TiN liner. "Co-containing" means containing elemental Co only or containing at least one of elemental Co and P or B. The Co-containing liner is formed by an electroless deposition process in order to provide the Co-containing liner of fine step coatability using the inside of the contact opening of a high aspect ratio. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过使用现有技术的MOL冶金及其制造方法来提供新的MOL冶金以避免缺陷。 解决方案：提供一种半导体结构，其包括布置在氧气吸气剂层和含有金属的导电材料之间的含Co衬里。 含Co的内衬，吸氧剂层和含有MOL冶金金属的导电材料，其中Co含量的衬垫取代了常规的TiN衬里。 “含Co”是指仅含有元素Co或含有元素Co和P或B中的至少一种。通过无电沉积方法形成含Co的内衬，以便使用 在高宽比的接触开口的内部。 版权所有（C）2007，JPO＆INPIT