公开(公告)号：AU2011285762B2

公开(公告)日：2016-02-04

申请号：AU2011285762

申请日：2011-08-03

Applicant: INTEL CORP

Inventor： SWANSON ROBERT C ,  BULUSU MALLIK ,  ZIMMER VINCENT J

IPC: G06F13/14 ,  G06F13/16 ,  G06F21/00

Abstract: In one embodiment, a peripheral controller coupled to a processor can include a storage controller. This storage controller can control access to a non-volatile storage coupled to the peripheral controller. The storage may include both secure and open partitions, and the storage controller can enable access to the secure partition only when the processor is in a secure mode. In turn, during unsecure operation such as third party code execution, visibility of the secure partition can be prevented. Other embodiments are described and claimed.

公开(公告)号：AU2011286271B2

公开(公告)日：2014-08-07

申请号：AU2011286271

申请日：2011-07-20

Applicant: INTEL CORP

Inventor： SWANSON ROBERT C ,  WEHAGE ERIC R ,  ZIMMER VINCENT J ,  BULUSU MALLIK

IPC: G06F9/48 ,  G06F11/08 ,  G06F12/00 ,  G06F12/16

Abstract: Methods and apparatus to protect segments of memory are disclosed herein. An example method includes intercepting an interrupt request indicating an error; determining whether a first segment of memory is corrupt, the first segment of memory being designated as a protected region of memory; when the protected region of memory is corrupt, repairing the corrupted region of memory using a parity block of code; and in response to validating the protected region of memory, generating an interrupt enabling a utilization of code stored in the protected region of memory to handle the error associated with the interrupt request.

公开(公告)号：AU2011305211B2

公开(公告)日：2014-07-03

申请号：AU2011305211

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： SWANSON ROBERT ,  ROTHMAN MICHAEL A ,  BULUSU MALLIK ,  ZIMMER VINCENT J ,  SAKTHIKUMAR PALSAMY

IPC: G06F9/06 ,  G06F9/22 ,  G06F13/14

Abstract: A network interface card with read-only memory having at least a micro-kernel of a cluster computing operation system, a server formed with such network interface card, and a computing cluster formed with such servers are disclosed herein. In various embodiments, on transfer, after an initial initialization phase during an initialization of a server, the network interface card loads the cluster computing operation system into system memory of the server, to enable the server, in conjunction with other similarly provisioned servers to form a computing cluster. Other embodiments are also disclosed and claimed.

公开(公告)号：AU2011305211A1

公开(公告)日：2013-03-07

申请号：AU2011305211

申请日：2011-09-23

Applicant: INTEL CORP

Inventor： SWANSON ROBERT ,  ROTHMAN MICHAEL A ,  BULUSU MALLIK ,  ZIMMER VINCENT J ,  SAKTHIKUMAR PALSAMY

IPC: G06F9/06 ,  G06F9/22 ,  G06F13/14

Abstract: A network interface card with read-only memory having at least a micro-kernel of a cluster computing operation system, a server formed with such network interface card, and a computing cluster formed with such servers are disclosed herein. In various embodiments, on transfer, after an initial initialization phase during an initialization of a server, the network interface card loads the cluster computing operation system into system memory of the server, to enable the server, in conjunction with other similarly provisioned servers to form a computing cluster. Other embodiments are also disclosed and claimed.

公开(公告)号：DE69838343T2

公开(公告)日：2008-05-21

申请号：DE69838343

申请日：1998-11-16

Applicant: INTEL CORP

Inventor： ZIMMER VINCENT J

IPC: G06F12/00 ,  G06F9/32 ,  G06F11/00 ,  G06F12/02

Abstract: The invention relates to the alteration of a segment and an offset used to form an effective address of the default interrupt handler routine. The method comprising a number of steps. First, a trap address of a default interrupt handler routine is provided. This trap address includes a segment and an offset normally used to calculate the effective address via conventional circuitry. However, an unique segment is produced by performing an arithmetic operation on the segment. Thereafter, another arithmetic operation is performed to produce a unique segment. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment and offset which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

公开(公告)号：AU1412099A

公开(公告)日：1999-07-05

申请号：AU1412099

申请日：1998-11-16

Applicant: INTEL CORP

Inventor： ZIMMER VINCENT J

IPC: G06F9/32 ,  G06F12/02 ,  G06F12/00 ,  G06F11/00

Abstract: The invention relates to the alteration of a segment and an offset used to form an effective address of the default interrupt handler routine. The method comprising a number of steps. First, a trap address of a default interrupt handler routine is provided. This trap address includes a segment and an offset normally used to calculate the effective address via conventional circuitry. However, an unique segment is produced by performing an arithmetic operation on the segment. Thereafter, another arithmetic operation is performed to produce a unique segment. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment and offset which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

公开(公告)号：WO2012040675A3

公开(公告)日：2012-07-12

申请号：PCT/US2011053165

申请日：2011-09-24

Applicant: INTEL CORP ,  SWANSON ROBERT C ,  DIAMANT NIMROD ,  ZIMMER VINCENT J ,  BULUSU MALLIK

Inventor： SWANSON ROBERT C ,  DIAMANT NIMROD ,  ZIMMER VINCENT J ,  BULUSU MALLIK

IPC: G06F9/22 ,  G06F9/06 ,  G06F13/14

CPC classification number: G06F9/4401 ,  G06F21/575 ,  G06F2221/2153

Abstract: Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the enumeration of the computer system by the BIOS, at least one configuration setting of the computer system to a management engine (ME) of the computer system; and applying a lock to the at least one configuration setting by the ME to manage a change to the at least one configuration setting, all prior to an ending of the POST.

Abstract translation: 一些方面包括通过计算机系统的BIOS开始自检（POST）; 用BIOS列举计算机系统; 基于所述计算机系统对所述计算机系统的枚举，将所述计算机系统的至少一个配置设置提供给所述计算机系统的管理引擎（ME）; 以及对所述ME的所述至少一个配置设置应用锁以管理所述至少一个配置设置的改变，所述更改在所述POST结束之前。

公开(公告)号：WO2012040694A3

公开(公告)日：2012-06-14

申请号：PCT/US2011053225

申请日：2011-09-26

Applicant: INTEL CORP ,  BAILEY ABDUL M ,  TANG DI ,  KHANNA RAHUL ,  ZIMMER VINCENT J ,  LI KEVIN Y ,  EDWARDS JAMES W

Inventor： BAILEY ABDUL M ,  TANG DI ,  ZIMMER VINCENT J ,  LI KEVIN Y ,  EDWARDS JAMES W

IPC: G06F13/14

CPC classification number: H04W76/02 ,  G06F9/4401 ,  G06F9/4411 ,  H04W4/001 ,  H04W4/003

Abstract: A system, device, and method for facilitating wireless communications during a pre-boot phase of a computing device includes establishing a communications interface between a unified extensible firmware interface executed on the computing device and a wireless transceiver of the computing device during a pre-boot phase of the computing device. An OOB processor of the computing device processes data communications between the unified extensible firmware interface and the wireless communication circuit during the pre-boot phase by reformatting the data communications between wired and wireless communication standards.

Abstract translation: 用于在计算设备的预引导阶段期间促进无线通信的系统，设备和方法包括在预启动期间在计算设备上执行的统一可扩展固件接口和计算设备的无线收发器之间建立通信接口 计算设备的阶段。 计算设备的OOB处理器通过重新格式化有线和无线通信标准之间的数据通信来在预引导阶段期间处理统一可扩展固件接口和无线通信电路之间的数据通信。

公开(公告)号：WO2012018889A3

公开(公告)日：2012-04-19

申请号：PCT/US2011046380

申请日：2011-08-03

Applicant: INTEL CORP ,  SWANSON ROBERT C ,  BULUSU MALLIK ,  ZIMMER VINCENT J

Inventor： SWANSON ROBERT C ,  BULUSU MALLIK ,  ZIMMER VINCENT J

IPC: G06F13/14 ,  G06F13/16 ,  G06F21/00

CPC classification number: G06F21/572 ,  G06F21/72 ,  G06F21/74 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2107 ,  G06F2221/2113 ,  G06F2221/2115

Abstract: In one embodiment, a peripheral controller coupled to a processor can include a storage controller. This storage controller can control access to a non-volatile storage coupled to the peripheral controller. The storage may include both secure and open partitions, and the storage controller can enable access to the secure partition only when the processor is in a secure mode. In turn, during unsecure operation such as third party code execution, visibility of the secure partition can be prevented. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，耦合到处理器的外围控制器可以包括存储控制器。 该存储控制器可以控制对耦合到外围控制器的非易失性存储器的访问。 存储可能包括安全和开放分区，只有当处理器处于安全模式时，存储控制器才可以访问安全分区。 反过来，在诸如第三方代码执行的不安全操作期间，可以防止安全分区的可见性。 描述并要求保护其他实施例。

公开(公告)号：WO2012012218A2

公开(公告)日：2012-01-26

申请号：PCT/US2011043638

申请日：2011-07-12

Applicant: INTEL CORP ,  XING BIN C ,  ZIMMER VINCENT J ,  ZMUDZINSKI KRYSTOF C

Inventor： XING BIN C ,  ZIMMER VINCENT J ,  ZMUDZINSKI KRYSTOF C

IPC: G06F9/22 ,  G06F9/06

CPC classification number: G06F9/4403

Abstract: In one embodiment, the present invention includes semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer. This code may include embedded memory code (EMC) to initialize a memory via initialization of a memory controller, and a mapping of memory signals using an on-die termination (ODT) data structure accessible via the EMC, where the ODT data structure is provided by an original equipment manufacturer (OEM) and corresponds to a parameterized rule set for a platform dependent memory configuration of the memory. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括对应于处理器制造商的平台无关代码的半导体集成代码（SIC）。 该代码可以包括通过初始化存储器控制器来初始化存储器的嵌入式存储器代码（EMC），以及使用可通过EMC访问的ODT数据结构的存储器信号的映射，其中ODT数据结构被提供 由原始设备制造商（OEM）提供，并且对应于存储器的平台相关存储器配置的参数化规则集。 描述并要求保护其他实施例。