公开(公告)号：US20190334533A1

公开(公告)日：2019-10-31

申请号：US16472835

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Elias Nassar ,  Eyal Fayneh ,  Inbar Falkov ,  Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Samer Nassar

IPC: H03L7/091 ,  H03L7/099

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

公开(公告)号：US10459407B1

公开(公告)日：2019-10-29

申请号：US16023973

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Elan Banin ,  Eran Ben Ami

IPC: G04F10/00 ,  H03L7/099 ,  H03M1/10 ,  H03M1/84

Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

公开(公告)号：US09419829B2

公开(公告)日：2016-08-16

申请号：US13669587

申请日：2012-11-06

Applicant: Intel Corporation

Inventor： Moshe Teplitsky ,  Michael Genossar ,  Elan Banin

IPC: H04L25/06

CPC classification number: H04L25/062 ,  H04L25/065

Abstract: Some demonstrative embodiments include devices, systems and/or methods of Direct Current (DC) estimation. For example, an apparatus may include an estimator to estimate a DC component of a received wireless communication packet based on a first value, a second value and an estimated frequency offset, wherein the first value is based on a first plurality of samples including at least a plurality of samples of a first sequence of a preamble of the wireless communication packet, the second value is based on a second plurality of samples including at least a plurality of samples of a second sequence of the preamble, immediately successive to the first sequence, and the estimated frequency offset corresponds to a frequency offset between the first and second pluralities of samples.

Abstract translation: 一些演示实施例包括直流（DC）估计的装置，系统和/或方法。 例如，装置可以包括估计器，用于基于第一值，第二值和估计的频率偏移来估计接收到的无线通信分组的DC分量，其中第一值基于至少包括第一多个样本 所述无线通信分组的前导码的第一序列的多个样本，所述第二值基于包括所述前导码的第二序列的至少多个采样的第二多个采样，所述第二序列紧接着所述第一序列， 并且估计的频率偏移对应于第一和第二多个样本之间的频率偏移。

公开(公告)号：US09106502B2

公开(公告)日：2015-08-11

申请号：US13680137

申请日：2012-11-19

Applicant: Intel Corporation

Inventor： Moshe Teplitsky ,  Elan Banin ,  Michael Genossar

IPC: H04L27/18 ,  H04L27/36 ,  H04L27/38 ,  H04B17/21 ,  H04B1/30

CPC classification number: H04L27/364 ,  H04B1/30 ,  H04B17/21 ,  H04L27/3863

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of In-phase/Quadrature (I/Q) imbalance compensation. For example, an apparatus may include an I/Q imbalance calibrator to determine, based on first and second phasors, a plurality of calibration parameters for calibrating I/Q imbalance of both a Radio Frequency (RF) Receive (Rx) path of a transceiver and a RF Transmit (Tx) path of the transceiver, the first phasor including a phasor of an image component of a first signal transmitted via the Tx path, shifted by a first phase shift and received via the Rx path, and the second phasor including a phasor of an image component of a second signal transmitted via the Tx path, shifted by a second phase shift, different from the first phase shift, and received via the Rx path.

Abstract translation: 一些演示实施例包括同相/正交（I / Q）不平衡补偿的装置，系统和/或方法。 例如，装置可以包括I / Q不平衡校准器，用于基于第一和第二相量确定用于校准收发器的射频（RF）接收（Rx）路径的I / Q不平衡的多个校准参数 和RF发射（Tx）路径，所述第一相量包括经由所述Tx路径发送的第一信号的图像分量的相量，偏移了第一相移并经由所述Rx路径接收，并且所述第二相量包括 经由Tx路径发送的第二信号的图像分量的相量，偏移与第一相移不同的第二相移，并且经由Rx路径接收。