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公开(公告)号:US11360933B2
公开(公告)日:2022-06-14
申请号:US16744407
申请日:2020-01-16
Applicant: Intel Corporation
Inventor: Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
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公开(公告)号:US11222392B2
公开(公告)日:2022-01-11
申请号:US16531763
申请日:2019-08-05
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
IPC: G06T1/20 , G06T1/60 , G09G5/36 , G06F3/06 , G06N3/08 , G06F3/14 , G06N3/04 , G06N3/063 , G09G5/00
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
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公开(公告)号:US20210294649A1
公开(公告)日:2021-09-23
申请号:US17206514
申请日:2021-03-19
Applicant: Intel Corporation
Inventor: Chandrasekaran Sakthivel , Prasoonkumar Surti , John C. Weast , Sara S. Baghsorkhi , Justin E. Gottschlich , Abhishek R. Appu , Nicolas C. Galoppo Von Borries , Joydeep Ray , Narayan Srinivasa , Feng Chen , Ben J. Ashbaugh , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Eriko Nurvitadhi , Balaji Vembu , Altug Koker
Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20210264163A1
公开(公告)日:2021-08-26
申请号:US17173732
申请日:2021-02-11
Applicant: Intel Corporation
Inventor: Mayuresh M. Varerkar , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Sherine Abdelhak , Sachin Godse , Farshad Akhbari , Narayan Srinivasa , Altug Koker , Nadathur Rajagopalan Satish , Dukhwan Kim , Feng Chen , Abhishek R. Appu , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Vasanth Ranganathan , Sanjeev Jahagirdar
Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
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公开(公告)号:US20210141649A1
公开(公告)日:2021-05-13
申请号:US17090295
申请日:2020-11-05
Applicant: Intel Corporation
Inventor: Li Xu , Haihao Xiang , Feng Chen , Travis Schluessler , Yuheng Zhang , Sen Lin
IPC: G06F9/448 , G06T1/20 , G06T1/60 , G06F16/215
Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
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公开(公告)号:US10922553B2
公开(公告)日:2021-02-16
申请号:US16379176
申请日:2019-04-09
Applicant: Intel Corporation
Inventor: Mayuresh M. Varerkar , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Sherine Abdelhak , Sachin Godse , Farshad Akhbari , Narayan Srinivasa , Altug Koker , Nadathur Rajagopalan Satish , Dukhwan Kim , Feng Chen , Abhishek R. Appu , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC: H04N5/225 , H04N3/20 , H04N5/228 , G06K9/00 , G06T1/20 , G06N3/04 , G06N3/08 , G06N3/063 , H04N7/14 , H04N5/38
Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.
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公开(公告)号:US10540318B2
公开(公告)日:2020-01-21
申请号:US15482796
申请日:2017-04-09
Applicant: Intel Corporation
Inventor: Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
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公开(公告)号:US20200019401A1
公开(公告)日:2020-01-16
申请号:US16444188
申请日:2019-06-18
Applicant: Intel Corporation
Inventor: Feng Chen , Narayan Srinivasa , Abhishek R. Appu , Altug Koker , Kamal Sinha , Balaji Vembu , Joydeep Ray , Nicolas C. Galoppo Von Borries , Prasoonkumar Surti , Ben J. Ashbaugh , Sanjeev Jahagirdar , Vasanth Ranganathan
IPC: G06F9/30 , G06F9/38 , G06F12/0862 , G06F9/50
Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.
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公开(公告)号:US10417731B2
公开(公告)日:2019-09-17
申请号:US15494886
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.
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公开(公告)号:US20190243764A1
公开(公告)日:2019-08-08
申请号:US16277267
申请日:2019-02-15
Applicant: Intel Corporation
Inventor: Chandrasekaran Sakthivel , Prasoonkumar Surti , John C. Weast , Sara S. Baghsorkhi , Justin E. Gottschlich , Abhishek R. Appu , Nicolas C. Galoppo Von Borries , Joydeep Ray , Narayan Srinivasa , Feng Chen , Ben J. Ashbaugh , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Eriko Nurvitadhi , Balaji Vembu , Altug Koker
IPC: G06F12/0837 , G06N20/00 , G06T1/20 , G06N3/08
CPC classification number: G06F12/0837 , G06F12/0815 , G06F2212/62 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084 , G06N3/088 , G06N20/00 , G06T1/20
Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
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