公开(公告)号：US12088360B2

公开(公告)日：2024-09-10

申请号：US16897135

申请日：2020-06-09

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Diego Correas-Serrano ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing ,  Cooper S. Levy ,  Chintan S. Thakkar ,  Stefano Pellerano

IPC: H04B3/32 ,  H04L25/03

CPC classification number: H04B3/32 ,  H04L25/03885

Abstract: Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed.

公开(公告)号：US11984439B2

公开(公告)日：2024-05-14

申请号：US16161578

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/0237

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

公开(公告)号：US20240063136A1

公开(公告)日：2024-02-22

申请号：US17891560

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Haris Khan Niazi ,  Yi Shi ,  Adel Elsherbini ,  Xavier Brun ,  Georgios Dogiamis ,  Thomas Brown ,  Omkar Karhade

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.

公开(公告)号：US11830831B2

公开(公告)日：2023-11-28

申请号：US16327810

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Johanna Swan ,  Shawna Liff ,  Adel Elsherbini ,  Telesphor Kamgaing ,  Aleksandar Aleksov

IPC: H01L23/66 ,  H01P3/12

CPC classification number: H01L23/66 ,  H01P3/121 ,  H01L2223/6627

Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.

公开(公告)号：US11784108B2

公开(公告)日：2023-10-10

申请号：US16533152

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/427 ,  H01L23/38 ,  H01L23/373 ,  H01L23/31 ,  H01L23/48 ,  H01L25/16 ,  H01L23/66 ,  H03H9/46 ,  H03H9/05

CPC classification number: H01L23/427 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/38 ,  H01L23/481 ,  H01L23/66 ,  H03H9/46 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20220399249A1

公开(公告)日：2022-12-15

申请号：US17346895

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H05K7/20 ,  H01L25/065

Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US20220190806A1

公开(公告)日：2022-06-16

申请号：US17688065

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H03H9/54 ,  H03H9/02 ,  H03H9/64

Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.

公开(公告)号：US20210408653A1

公开(公告)日：2021-12-30

申请号：US16911568

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16 ,  H01P1/20 ,  H01P5/08 ,  H01P1/208

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US20210400856A1

公开(公告)日：2021-12-23

申请号：US16909269

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01B7/00 ,  H01B7/18 ,  H01R12/53

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

公开(公告)号：US20210398909A1

公开(公告)日：2021-12-23

申请号：US16905202

申请日：2020-06-18

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Feras Eid ,  Adel Elsherbini ,  David Johnston ,  Jyothi Bhaskarr Velamala ,  Rachael Parker

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/498 ,  H04L9/32

Abstract: Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.