公开(公告)号：WO1997024681A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020315

申请日：1996-12-18

Applicant: INTEL CORPORATION ,  MENNEMEIER, Larry, M. ,  PELEG, Alexander, D. ,  MITTAL, Millind ,  EITAN, Benny ,  DULONG, Carole ,  KOWASHI, Eiichi

Inventor： INTEL CORPORATION

IPC: G06F15/00

CPC classification number: G06T3/60 ,  G06F15/7864

Abstract: A computer system (100) includes a processor (109), a multimedia input device (122) receiving an analog signal representing an image or audio input, and a digitizing unit (126) coupled to the multimedia input device (109). The computer system (100) further includes a memory (104) coupled to the digitizing unit (126) and the processor (109). The memory (104) has stored therein a set of packed data sequences having data elements representing the digital data, and a sequence of instructions for transforming the digital data from a first domain to a second domain. When the instructions are executed by the processor (109), the instructions cause the processor (109) to perform a two-dimensional rotation on the digital data. Specifically, the instructions cause the processor (109) to generate a first set of intermediate results by multiplying data elements of a first packed data sequence with corresponding elements of a third packed data sequence represent either a sine or cosine function. The instructions then cause the processor (109) to generate a second set of intermediate results by multiplying the data elements of a second packed data sequence with corresponding data elements of a fourth packed data sequence representing either a sine or cosine function. A set of first set of final results by performing an arithmetic operation between corresponding data elements of the first and second sets of intermediate results.

Abstract translation: 计算机系统（100）包括处理器（109），接收表示图像或音频输入的模拟信号的多媒体输入设备（122）和耦合到多媒体输入设备（109）的数字化单元（126）。 计算机系统（100）还包括耦合到数字化单元（126）和处理器（109）的存储器（104）。 存储器（104）在其中存储了一组具有表示数字数据的数据元素的打包数据序列，以及用于将数字数据从第一域变换到第二域的指令序列。 当处理器（109）执行指令时，指令使处理器（109）对数字数据执行二维旋转。 具体地，指令使处理器（109）通过将第一打包数据序列的数据元素与表示正弦或余弦函数的第三打包数据序列的相应元素相乘来产生第一组中间结果。 然后，指令使处理器（109）通过将第二打包数据序列的数据元素与表示正弦或余弦函数的第四打包数据序列的相应数据元素相乘来产生第二组中间结果。 通过在第一组和第二组中间结果的相应数据元素之间执行算术运算来生成一组第一组最终结果。

公开(公告)号：WO1997024677A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020815

申请日：1996-12-27

Applicant: INTEL CORPORATION ,  GILLESPIE, Byron ,  GOLDSCHMIDT, Marc ,  SYCH, Terry ,  YOUNG, Bruce

Inventor： INTEL CORPORATION

IPC: G06F13/00

CPC classification number: G06F13/105 ,  G06F13/404

Abstract: A method and apparatus for interfacing a device (8) which is compliant to a first bus protocol to a second bus (11) having a second protocol and for providing virtual functions through an intelligent bridge (9) that is coupled to the second bus (11). An address translator (35), coupled to the second bus (11), for translating addresses in a second bus format into addresses in a first bus format is provided. A device selection detection circuit (37) is provided for detecting that a configuration cycle from the second bus (11) is for that particular device. Once a configuration cycle is detected, interrupt generation circuitry (43) interrupts a local processor (29), coupled to the first local processor bus (13). The device selection detection circuitry (37) also writes to a register (41) disposed in a configuration controller (39). The configuration controller (39) disables the address translator (35) so that any further accesses to the local processor bus (13) are blocked.

Abstract translation: 一种用于将符合第一总线协议的设备（8）连接到具有第二协议的第二总线（11）并用于通过耦合到第二总线的智能桥（9）提供虚拟功能的方法和装置 11）。 提供一种耦合到第二总线（11）的地址转换器（35），用于将第二总线格式的地址转换成第一总线格式的地址。 提供了一种用于检测来自第二总线（11）的配置周期用于该特定设备的设备选择检测电路（37）。 一旦检测到配置周期，中断产生电路（43）中断耦合到第一本地处理器总线（13）的本地处理器（29）。 设备选择检测电路（37）还写入配置控制器（39）中设置的寄存器（41）。 配置控制器（39）禁用地址转换器（35），使得对本地处理器总线（13）的任何进一步访问都被阻止。

公开(公告)号：WO1997024656A1

公开(公告)日：1997-07-10

申请号：PCT/US1996020809

申请日：1996-12-27

Applicant: INTEL CORPORATION ,  THURLO, Clark, S.

Inventor： INTEL CORPORATION

IPC: G06F07/00

CPC classification number: G06F9/4415 ,  G06F13/102

Abstract: A peripheral device (106, 107, 108) for use in interfacing with a system (100). The peripheral device (106, 107, 108) contains driver code stored in memory locations within the peripheral device (106, 107, 108). The driver code is uncompiled, and, when read by a system (100) to which the peripheral device (106, 107, 108) is coupled, enables the system (100) to interface with the peripheral device (106, 107, 108).

Abstract translation: 一种用于与系统（100）进行接口连接的外围设备（106,107,108）。 外围设备（106,107,108）包含存储在外围设备（106,107,108）内的存储器位置的驱动程序代码。 驱动程序代码未被编译，并且当被外围设备（106,107,108）耦合到的系统（100）读取时，系统（100）能够与外围设备（106,107,108）接口， 。

公开(公告)号：WO1997023831A1

公开(公告)日：1997-07-03

申请号：PCT/US1996020104

申请日：1996-12-20

Applicant: INTEL CORPORATION ,  HAMNER, John, F. ,  JANICH, Sandra ,  DESPAIN, Jeffrey, L. ,  NIEMANN, Katherine, D. ,  SEVY, Brian, D. ,  TRAN, Dzung, D. ,  WELCH, Frank, K.

Inventor： INTEL CORPORATION

IPC: G06F13/00

CPC classification number: H04L41/22 ,  H04L41/0233 ,  H04L41/024 ,  H04L41/0893 ,  H04L41/12 ,  H04L41/20 ,  Y10S707/99943 ,  Y10S707/99944 ,  Y10S707/99945

Abstract: A computer-implemented method of managing a computer network including a plurality of devices is provided, wherein a plurality of network management tasks are performable upon the devices. Data is gathered about a present configuration of the network, including the types of devices in the network, the quantity of each type of device present in the network, the relationships between the devices, and the tasks performable upon each of the devices. The data is then stored in a database representing a network map. A display is generated corresponding to the network map using the data in the database (200). The display shows an association of the devices (201) with the tasks performable on the devices (202) using bitmap representations (205, 207) of the devices and tasks. The display may include hierarchical, schematic, or geographical representations of the devices on the network (201). The devices are organized into a plurality of groups. In response to a user input selecting a device or group, the tasks performable by that device or group are identified on the display (209, 211). A user may initiate any one of the displayed tasks by applying a user input selecting that task.

Abstract translation: 提供了一种管理包括多个设备的计算机网络的计算机实现的方法，其中可以对所述设备执行多个网络管理任务。 收集关于网络的当前配置的数据，包括网络中的设备类型，网络中存在的每种类型的设备的数量，设备之间的关系以及在每个设备上可执行的任务。 然后将数据存储在代表网络图的数据库中。 使用数据库（200）中的数据，对应于网络映射生成显示。 显示器使用设备和任务的位图表示（205,207）显示设备（201）与在设备（202）上可执行的任务的关联。 显示器可以包括网络（201）上的设备的分级，示意图或地理表示。 设备被组织成多个组。 响应于用户输入选择设备或组，在显示器（209,211）上识别由该设备或组可执行的任务。 用户可以通过应用选择该任务的用户输入来启动任何一个显示的任务。

公开(公告)号：WO1997023830A1

公开(公告)日：1997-07-03

申请号：PCT/US1996011586

申请日：1996-07-12

Applicant: INTEL CORPORATION ,  CROCKER, Ken, M. ,  VENKATARAMAN, Radhakrishnan ,  WADE, Nicholas

Inventor： INTEL CORPORATION

IPC: G06F12/06

CPC classification number: G06F12/0223 ,  G09G5/39 ,  G09G2360/125

Abstract: A method and system for dynamically sizing (50, 51, 52, 53, 54, 55, 56) a dedicated memory in a shared memory buffer architecture (4). At initial boot, system BIOS programs control register (22, 23, 24) to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers (22, 23, 24), the dedicated memory size is dynamically changed without any manual manipulation of internal components.

Abstract translation: 一种用于在共享存储器缓冲器架构（4）中动态地调整（50,51,52,53,54,55,56）专用存储器的方法和系统。 在初始启动时，系统BIOS程序控制寄存器（22,23,24）分配所需大小的专用存储器。 分配的专用内存的大小取决于性能要求。 如果在初始引导后，性能要求发生变化，则可能需要更改专用内存大小。 通过重新编程控制寄存器（22,23,24），专门的存储器大小是动态地改变的，而不需要任何手动操纵内部组件。

公开(公告)号：WO1997022990A1

公开(公告)日：1997-06-26

申请号：PCT/US1996019808

申请日：1996-12-12

Applicant: INTEL CORPORATION ,  ROLLENDER, Matthew ,  HIRT, Ray

Inventor： INTEL CORPORATION

IPC: H01L21/02

CPC classification number: H01L27/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/24 ,  H01L23/573 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48137 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method for securing confidential circuitry from observation by unauthorized inspection, and a secure circuit immune from unauthorized inspection according to the method. In one embodiment, confidential data or circuitry is placed on a face of separate silicon layers (42, 44), each silicon layer having part of a circuit. Neither silicon layer is intelligible without the other, yet neither can be observed without destroying the other. The two silicon layers are juxtaposed, the face of the first silicon layer (42) flush against and fused to the face of the second silicon layer (44), the confidential circuits on each silicon layer connecting directly with circuits on the other silicon layer without external connectors. Data stored on each face is erased or destroyed when the silicon layers are separated or one of the silicon layers is destroyed. Violence to either silicon layer, or exposure of either silicon layer to light, destroys the data or circuitry on at least one silicon layer of silicon, making the data or circuitry unreadable.

Abstract translation: 一种用于通过未经授权的检查来保护机密电路免于观察的方法，以及根据该方法免于未经授权的检查的安全电路。 在一个实施例中，机密数据或电路放置在单独硅层（42,44）的表面上，每个硅层具有电路的一部分。 没有一个硅层是不可理解的，但是两者都不能在没有破坏另一个的情况下被观察到。 两个硅层并置，第一硅层（42）的表面与第二硅层（44）的表面齐平并熔合，每个硅层上的保密电路直接与另一个硅层上的电路连接，而没有 外部连接器 当硅层分离或硅层中的一个被破坏时，存储在每个面上的数据被擦除或破坏。 暴露于硅层或将硅层暴露于光，会破坏至少一个硅层的硅层上的数据或电路，从而使数据或电路无法读取。

公开(公告)号：WO1997022924A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020573

申请日：1996-12-17

Applicant: INTEL CORPORATION ,  GLEW, Andrew, F. ,  VAKKALAGADDA, Ramamohan, R. ,  LIN, Derrick ,  MENNEMEIER, Larry, M. ,  PELEG, Alexander, D. ,  BISTRY, David ,  MITTAL, Millind ,  DULONG, Carole ,  KOWASHI, Eiichi ,  EITAN, Benny

Inventor： INTEL CORPORATION

IPC: G06F09/34

CPC classification number: G06F9/3017 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/45533 ,  G06F9/462

Abstract: A method for executing different sets of instructions that cause a processor (105) to perform different data type operations in a manner that is invisible to various operating system techniques. According to one embodiment of the invention, a data processing apparatus (105) executes a first set of instructions of a first data type on what at least logically appears to software as a single logical register file (310), which appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second data type using the logical register file (300), which appears to be operating as a stack referenced register file (340). Furthermore, the data processing apparatus alters all tags in a set of tags (320, 330) corresponding to the single logical register file (300, 310) to a non-empty state some time between starting the execution of the first set of instructions and completing the execution of the first instruction.

Abstract translation: 一种用于执行使得处理器（105）以对各种操作系统技术不可见的方式执行不同数据类型操作的不同指令集的方法。 根据本发明的一个实施例，数据处理装置（105）执行第一数据类型的第一组指令，至少逻辑上显示为软件，作为单个逻辑寄存器文件（310），其似乎被操作为 一个平面寄存器文件。 此外，数据处理装置使用看起来作为堆栈引用的寄存器文件（340）操作的逻辑寄存器文件（300）来执行第二数据类型的第一指令。 此外，在开始执行第一组指令之前的某个时刻，数据处理装置将对应于单个逻辑寄存器文件（300,310）的一组标签（320,330）中的所有标签改变为非空状态，以及 完成第一条指令的执行。

公开(公告)号：WO1997022923A1

公开(公告)日：1997-06-26

申请号：PCT/US1996020572

申请日：1996-12-17

Applicant: INTEL CORPORATION ,  ORENSTEIN, Doron ,  VAKKALAGADDA, Ramamohan, R. ,  GLEW, Andrew, F. ,  MENNEMEIER, Larry, M. ,  PELEG, Alexander, D. ,  BISTRY, David ,  MITTAL, Millind ,  DULONG, Carole ,  KOWASHI, Eiichi ,  EITAN, Benny ,  WECHSLER, Ofri ,  LIN, Derrick

Inventor： INTEL CORPORATION

IPC: G06F09/34

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30192 ,  G06F9/3861

Abstract: A method and apparatus for executing different sets of instructions that cause a processor (105) to perform different data type operations on different physical register file (615, 650) that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor (105) is provided that includes at least two physical register files (615, 650) -one for executing scalar data type operations (615) and the other for executing packed data type operations (650). In addition, the processor (105) includes a transition unit (600) that is configured to cause two physical register files (615, 650) to logically appear to software executing on the processor (105) as a single register file.

Abstract translation: 一种用于执行不同指令集的方法和装置，其使处理器（105）在逻辑上以软件形式显示为单个混叠寄存器文件的不同物理寄存器文件（615,650）上执行不同的数据类型操作。 根据本发明的一个方面，提供一种处理器（105），其包括用于执行标量数据类型操作（615）的至少两个物理寄存器文件（615,650），另一个用于执行打包数据类型操作（650 ）。 另外，处理器（105）包括转移单元（600），其被配置为使得两个物理寄存器文件（615,650）在处理器（105）上作为单个寄存器文件逻辑出现在执行软件上。

公开(公告)号：WO1997022123A1

公开(公告)日：1997-06-19

申请号：PCT/US1996019841

申请日：1996-12-10

Applicant: INTEL CORPORATION ,  FAZIO, Albert ,  ATWOOD, Gregory, E. ,  MI, James, O. ,  RUBY, Paul

Inventor： INTEL CORPORATION

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5621

Abstract: In a memory device including an array of memory cells, each memory cell having more than two possible states, a method for programming a memory cell to a desired state is disclosed. The method comprises a control engine programming a subset (220), wherein the characterization information indicates programming characteristics of a representative memory cell of the array of memory cells (225). The control engine then uses the characterization information to directly program the memory cell to approximately the desired state (230) without performing a program verify operation.

Abstract translation: 在包括存储器单元阵列的存储器件中，每个存储器单元具有两个以上的可能状态，公开了一种用于将存储器单元编程到期望状态的方法。 该方法包括编程子集（220）的控制引擎，其中表征信息指示存储器单元阵列（225）的代表性存​​储单元的编程特性。 然后，控制引擎使用表征信息将存储器单元直接编程到大致期望的状态（230），而不执行程序验证操作。

公开(公告)号：WO1997021290A1

公开(公告)日：1997-06-12

申请号：PCT/US1996019025

申请日：1996-11-27

Applicant: INTEL CORPORATION ,  DAVIS, Derek, L.

Inventor： INTEL CORPORATION

IPC: H04K01/00

CPC classification number: G06F21/445 ,  G06F21/34 ,  G06F2211/009

Abstract: A mechanism to conditionally activate an electronic device implemented within electronic computing equipment such as a computer. Such activation may be based on user authentication and/or confirmation that the electronic device is operating in conjunction with its companion cryptographic device (130).

Abstract translation: 用于有条件地激活在诸如计算机的电子计算设备内实现的电子设备的机制。 这种激活可以基于用户认证和/或确认电子设备与其伴侣密码设备（130）一起操作。