公开(公告)号：US20190355636A1

公开(公告)日：2019-11-21

申请号：US16526497

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US10410939B2

公开(公告)日：2019-09-10

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20190051447A1

公开(公告)日：2019-02-14

申请号：US16162465

申请日：2018-10-17

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Yikang Deng

IPC: H01F27/28 ,  H01F27/255 ,  C25D5/48 ,  H01F41/04 ,  H01F41/02 ,  C25D5/16 ,  H01F17/00 ,  C25D7/00

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US10085341B2

公开(公告)日：2018-09-25

申请号：US15461406

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K7/10 ,  H05K1/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/20 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

公开(公告)号：US20180213655A1

公开(公告)日：2018-07-26

申请号：US15927366

申请日：2018-03-21

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H05K3/10 ,  H01L23/538 ,  H05K1/18

CPC classification number: H05K3/4647 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/185 ,  H05K3/108 ,  H05K3/465 ,  H05K2203/0733 ,  H01L2924/00

Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

公开(公告)号：US10008451B2

公开(公告)日：2018-06-26

申请号：US15445805

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L21/4763 ,  H01L23/538 ,  H01L23/00 ,  H01L21/02 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

公开(公告)号：US09899311B2

公开(公告)日：2018-02-20

申请号：US15370432

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48 ,  H05K1/16

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20170221828A1

公开(公告)日：2017-08-03

申请号：US15445805

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

公开(公告)号：US20170187419A1

公开(公告)日：2017-06-29

申请号：US14998254

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Zhang ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Henning Braunisch ,  Kemal Aygun

IPC: H04B3/32 ,  H04L5/14

CPC classification number: H04B3/32 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.

公开(公告)号：US20170162509A1

公开(公告)日：2017-06-08

申请号：US15438321

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/147 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/1412 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/24146 ,  H01L2224/2541 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.