公开(公告)号：US10915468B2

公开(公告)日：2021-02-09

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US20200210366A1

公开(公告)日：2020-07-02

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20190108124A1

公开(公告)日：2019-04-11

申请号：US16140482

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/42 ,  G06F13/16

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US09921768B2

公开(公告)日：2018-03-20

申请号：US14576125

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Debendra Das Sharma ,  Mahesh Wagh ,  Venkatraman Iyer

IPC: G06F3/06 ,  G06F13/38 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/3234 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/385

Abstract: Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

公开(公告)号：US20170091003A1

公开(公告)日：2017-03-30

申请号：US14866955

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Joseph Murray

IPC: G06F9/54 ,  G06F13/42 ,  G06F13/24

CPC classification number: G06F9/546 ,  G06F13/24 ,  G06F13/4282

Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.

公开(公告)号：US20160179427A1

公开(公告)日：2016-06-23

申请号：US14576125

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Debendra Das Sharma ,  Mahesh Wagh ,  Venkatraman Iyer

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/3234 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/385

Abstract: Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

Abstract translation: 根据存储器访问链路协议，数据被发送以对应于通过链路与共享存储器相关联的加载/存储类型操作，并且存储器访问链路协议将被覆盖在另一不同的链路协议上。 发送请求进入低功率状态，其中请求包括在令牌的字段中编码的数据值，令牌是指示分组数据的开始，并且进一步指示是否在后发送的后续数据 令牌是根据其他链路协议和存储器访问链路协议之一来包括数据。