公开(公告)号：EP4264667A1

公开(公告)日：2023-10-25

申请号：EP21907382.2

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  DUAN, Gang ,  VADLAMANI, Sai ,  PENMECHA, Bharat Prasad

IPC: H01L23/538 ,  H01L23/14

公开(公告)号：EP4248249A1

公开(公告)日：2023-09-27

申请号：EP21895299.2

申请日：2021-09-09

Applicant: INTEL Corporation

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

公开(公告)号：EP4156256A1

公开(公告)日：2023-03-29

申请号：EP22197128.6

申请日：2022-09-22

Applicant: INTEL Corporation

Inventor： ALEKSOV, Aleksandar ,  DARMAWIKARTA, Kristof Kuwawi ,  PIETAMBARAM, Srinivas V.

IPC: H01L23/498 ,  H01L21/48

Abstract: Glass layers having partially embedded conductive layers for power delivery in semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer having a thickness between a first surface opposite a second surface. The core layer includes a trench provided in the first surface. The trench partially extending between the first surface and the second surface. An electrically conductive material is positioned in the trench. A trace is provided on the conductive material. The trace is offset in a direction away from the first surface and away from the second surface of the core layer.

公开(公告)号：EP4016151A1

公开(公告)日：2022-06-22

申请号：EP21198382.0

申请日：2021-09-22

Applicant: INTEL Corporation

Inventor： DESHPANDE, Nitin ,  KARHADE, Omkar ,  MARIN, Brandon ,  MAY, Robert ,  BOYAPATI, Sri Ranga Sai ,  PIETAMBARAM, Srinivas V. ,  LI, Xiaoqian ,  ECTON, Jeremy ,  PRATAP, Divya ,  TANAKA, Hiroki ,  VADLAMANI, Sai

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

公开(公告)号：EP3961701A1

公开(公告)日：2022-03-02

申请号：EP21198092.5

申请日：2020-02-10

Applicant: INTEL Corporation

Inventor： PIETAMBARAM, Srinivas V. ,  DUAN, Gang ,  KULKARNI, Deepak ,  MANEPALLI, Rahul N. ,  GUO, Xiaoying

IPC: H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages.

公开(公告)号：EP4184569A3

公开(公告)日：2023-08-09

申请号：EP22201685.9

申请日：2022-10-14

Applicant: INTEL Corporation

Inventor： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC: H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

Abstract: In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP4156255A1

公开(公告)日：2023-03-29

申请号：EP22191777.6

申请日：2022-08-23

Applicant: INTEL Corporation

Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  COLLINS, Andrew

IPC: H01L23/498 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

公开(公告)号：EP4155788A1

公开(公告)日：2023-03-29

申请号：EP22191139.9

申请日：2022-08-19

Applicant: INTEL Corporation

Inventor： NIE, Bai ,  TADAYON, Pooya ,  ARANA, Leonel ,  LI, Yonggang ,  LIU, Changhua ,  DARMAWIKARTA, Kristof Kuwawi ,  PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  MAHALINGAM, Hari ,  DUONG, Benjamin

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/30 ,  G02B6/42

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic integrated circuit and an in situ formed waveguide. In selected examples, the electronic device includes a photonic integrated circuit coupled to an electronic integrated circuit, in a glass layer, where a waveguide is formed in the glass layer.

公开(公告)号：EP4152060A1

公开(公告)日：2023-03-22

申请号：EP22189557.6

申请日：2022-08-09

Applicant: INTEL Corporation

Inventor： DARMAWIKARTA, Kristof ,  PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  MAHALINGAM, Hari ,  DUONG, Benjamin ,  NIE, Bai

IPC: G02B6/122 ,  G02B6/132 ,  G02B6/136

Abstract: Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

公开(公告)号：EP3485510A1

公开(公告)日：2019-05-22

申请号：EP17828153.1

申请日：2017-06-22

Applicant: INTEL Corporation

Inventor： BOYAPATI, Sri Ranga Sai ,  MANEPALLI, Rahul N. ,  SENEVIRATNE, Dilan ,  PIETAMBARAM, Srinivas V. ,  DARMAWIKARTA, Kristof ,  MAY, Robert Alan ,  SALAMA, Islam A.

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065