公开(公告)号：US11677017B2

公开(公告)日：2023-06-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82 ,  H01L29/43

CPC classification number: H01L29/66977 ,  G06N10/00 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/158 ,  H01L29/66984 ,  H01L29/7831 ,  H01L29/82 ,  H01L29/437

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20220059656A1

公开(公告)日：2022-02-24

申请号：US17453088

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US11195919B2

公开(公告)日：2021-12-07

申请号：US16148621

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/04 ,  H01L29/165 ,  H01L27/12 ,  H01L27/092

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US11158731B2

公开(公告)日：2021-10-26

申请号：US16642886

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20200350423A1

公开(公告)日：2020-11-05

申请号：US16642886

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/15 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20200321436A1

公开(公告)日：2020-10-08

申请号：US16650299

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC: H01L29/15 ,  G06N10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

公开(公告)号：US10790281B2

公开(公告)日：2020-09-29

申请号：US15773325

申请日：2015-12-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Roza Kotlyar ,  Stephen M. Cea ,  Patrick H. Keys

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/06 ,  H01L29/78 ,  H01L21/822 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

公开(公告)号：US10600787B2

公开(公告)日：2020-03-24

申请号：US16078675

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Peter G. Tolchinsky ,  Roza Kotlyar ,  Valluri R. Rao

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8258 ,  H01L23/498 ,  H01L23/544 ,  H01L29/16 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/417 ,  H01L21/8238 ,  H04B1/38

Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.

公开(公告)号：US09876014B2

公开(公告)日：2018-01-23

申请号：US15270795

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/283 ,  H01L29/15 ,  H01L29/775 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US09871106B2

公开(公告)日：2018-01-16

申请号：US15037296

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Roza Kotlyar ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Ian A. Young

IPC: H01L29/76 ,  H01L29/12 ,  H01L29/739 ,  G11C5/06 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.