公开(公告)号：EP3123337B1

公开(公告)日：2018-06-13

申请号：EP15769624.6

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  NEMIROFF, Daniel ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  LINDSLEY, John R. ,  CONE, Robert W. ,  TRIVEDI, Malay ,  KWIDZINSKI, Piotr

IPC: G06F12/02 ,  G06F13/28 ,  G06F21/57 ,  G06F3/06 ,  G06F21/55 ,  H04L29/06

CPC classification number: H04L63/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0683 ,  G06F13/28 ,  G06F21/554 ,  G06F21/57 ,  G06F21/572

Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

公开(公告)号：EP2601588B1

公开(公告)日：2018-05-23

申请号：EP11815248.7

申请日：2011-08-03

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  BULUSU, Mallik ,  ZIMMER, Vincent J.

IPC: G06F13/14 ,  G06F13/16 ,  G06F21/72 ,  G06F21/57 ,  G06F21/79 ,  G06F21/74 ,  G06F21/85

CPC classification number: G06F21/572 ,  G06F21/72 ,  G06F21/74 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2107 ,  G06F2221/2113 ,  G06F2221/2115

Abstract: In one embodiment, a peripheral controller coupled to a processor can include a storage controller. This storage controller can control access to a non-volatile storage coupled to the peripheral controller. The storage may include both secure and open partitions, and the storage controller can enable access to the secure partition only when the processor is in a secure mode. In turn, during unsecure operation such as third party code execution, visibility of the secure partition can be prevented. Other embodiments are described and claimed.

公开(公告)号：EP3060980A1

公开(公告)日：2016-08-31

申请号：EP13895862.4

申请日：2013-10-24

Applicant: Intel Corporation

Inventor： ZIMMER, Vincent J. ,  ROTHMAN, Michael A. ,  BAHNSEN, Robert B. ,  SWANSON, Robert C.

IPC: G06F9/22 ,  G06F9/24

CPC classification number: G06F9/445 ,  G06F8/52 ,  G06F8/65 ,  G06F8/654 ,  G06F9/22 ,  G06F9/24 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45516 ,  G06F21/572 ,  G06F21/575 ,  G06F2221/033

Abstract: Methods and apparatus relating to pre-OS (pre Operating System) image rewriting to provide cross-architecture support, security introspection, and/or performance optimization are described. In an embodiment, logic rewrites a non-native firmware interface driver into a native firmware interface driver in response to a determination that sufficient space is available in an integrity cache storage device to store the native firmware interface driver. The logic rewrites the non-native firmware interface driver into the native firmware interface driver by performing one or more of its operations during operating system runtime. Other embodiments are also claimed and described.

Abstract translation: 的方法和设备有关的预操作系统（预先操作系统）图像改写，以提供跨架构支持，安全自省，和/或性能优化的描述。 ，实施例逻辑重写的非天然固件接口驱动程序转换成本机固件接口驱动器在响应于确定没有足够的空间是可用在完整性缓存存储装置以存储的本机固件接口驱动程序。 该逻辑由操作系统运行时间期间执行其操作中的一个或多个重写非天然固件接口驱动到天然固件接口驱动程序。 因此其它实施例中要求保护和描述。

公开(公告)号：EP2622533B1

公开(公告)日：2015-11-18

申请号：EP11830034.2

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： SAKTHIKUMAR, Palsamy ,  SWANSON, Robert C. ,  ROTHMAN, Michael A. ,  BULUSU, Mallik ,  ZIMMER, Vincent J.

IPC: G06F13/14 ,  G06F9/22 ,  G06F9/44 ,  G06F21/57

CPC classification number: G06F13/105 ,  G06F9/4812 ,  G06F21/572 ,  G06F2221/2105

公开(公告)号：EP2601587B1

公开(公告)日：2015-11-18

申请号：EP11814988.9

申请日：2011-07-18

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  ROTHMAN, Michael A. ,  SAKTHIKUMAR, Palsamy

IPC: H04W84/18 ,  H04W4/00 ,  H04L12/751

CPC classification number: H04L45/02 ,  H04W4/80 ,  H04W84/18

Abstract: Radio frequency identification (RFID) tags embedded in processors within a computing system provide a separate communication path to other components of the computing system during initialization processing, apart from the system interconnect. Upon powering up, each processor causes its RFID tag to broadcast data regarding the processor's interconnect location and initialization status. A RFID receiver senses the RFID tags in the Platform Control Hub (PCH), and each processor's interconnect location and initialization status data is stored in registers within the PCH. During system initialization processing, the BIOS accesses these PCH registers to obtain the processor's data. The interconnect location and initialization status data is used by the BIOS to select the optimal routing table and configure the virtual network within the computing system based on the optimal routing table and the RFID tag data, without interrogating each processor individually over the system interconnect.

公开(公告)号：EP3404947A1

公开(公告)日：2018-11-21

申请号：EP18181004.5

申请日：2011-12-30

Applicant: INTEL Corporation

Inventor： BULUSU, Mallik ,  BAHNSEN, Robert ,  ZIMMER, Vincent J. ,  GITTINS, Robert S. ,  SWANSON, Robert C.

IPC: H04W12/08 ,  H04W12/06 ,  H04L29/06

CPC classification number: H04L63/0876 ,  G06F21/00 ,  H04L63/08 ,  H04W12/06 ,  H04W12/08

Abstract: An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform "context migration" to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.

公开(公告)号：EP3392774A1

公开(公告)日：2018-10-24

申请号：EP18177232.8

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  NEMIROFF, Daniel ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  LINDSLEY, John R. ,  CONE, Robert W. ,  TRIVEDI, Malay ,  KWIDZINSKI, Piotr

IPC: G06F12/02 ,  G06F13/28 ,  G06F21/57 ,  G06F3/06 ,  G06F21/55 ,  H04L29/06

CPC classification number: H04L63/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0683 ,  G06F13/28 ,  G06F21/554 ,  G06F21/57 ,  G06F21/572

Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

公开(公告)号：EP3158452A1

公开(公告)日：2017-04-26

申请号：EP15812152.5

申请日：2015-05-14

Applicant: Intel Corporation

Inventor： MUDUSURU, Giri P. ,  ZIMMER, Vincent J. ,  KOTARY, Karunakara ,  STORY, Ronald N. ,  SWANSON, Robert C. ,  ORAM, Isaac W.

IPC: G06F11/14 ,  G06F9/44 ,  G06F9/445

CPC classification number: G06F1/30 ,  G06F11/1441 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/1416 ,  G06F12/1491 ,  G06F13/32 ,  G06F2212/1024 ,  G06F2212/222 ,  G11C5/141

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.

Abstract translation: 通常，本公开提供了具有持久存储器的统一可扩展固件接口（UEFI）的系统，设备，方法和计算机可读介质，以提供例如在电力丢失的情况下的存储器写持续性。 该系统可以包括处理器以承载固件接口，其可被配置为控制对易失性存储器的受保护区域中的系统变量的访问。 该系统还可以包括功率管理电路，以向处理器提供电力，并进一步向固件接口提供功率损耗指示符。 系统还可以包括备用能量存储模块，以响应于功率损耗指示器向处理器提供电力。 固件接口还被配置为响应于功率损耗指示器将系统变量从易失性存储器复制到非易失性存储器。

公开(公告)号：EP3123337A1

公开(公告)日：2017-02-01

申请号：EP15769624.6

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  NEMIROFF, Daniel ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  LINDSLEY, John R. ,  CONE, Robert W. ,  TRIVEDI, Malay ,  KWIDZINSKI, Piotr

IPC: G06F12/02 ,  G06F13/16

CPC classification number: H04L63/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0683 ,  G06F13/28 ,  G06F21/554 ,  G06F21/57 ,  G06F21/572

Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了用于信任操作的多节点集线器的实施例。 在一些实施例中，多节点集线器可以包括多个存储器区域，陷阱模块和可信平台模块（TPM）组件。 每个存储器区域可以与相干计算节点相关联并接收来自相干计算节点的信任操作数据。 捕获模块可以响应于相关联的相干计算节点对多个存储器区域的访问而产生陷阱通知。 陷阱通知可以指示已经访问了多个存储器位置中的哪一个，并且TPM组件可以处理由陷阱通知指示的存储器区域中的信任操作数据。 可以公开和/或要求保护其他实施例。

公开(公告)号：EP3123299A1

公开(公告)日：2017-02-01

申请号：EP15769354.0

申请日：2015-01-28

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  TRAW, C. Brendan ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  LINDSLEY, John R. ,  NATU, Mahesh S. ,  ZIAKAS, Dimitrios ,  CONE, Robert W. ,  RANGARAJAN, Madhusudhan ,  NIKJOU, Babak ,  BRANNOCK, Kirk D. ,  WUNDERLICH, Russell J. ,  SCHWARTZ, Miles F. ,  PAWLOWSKI, Stephen S.

IPC: G06F9/22 ,  G06F11/30

CPC classification number: G06F11/3476 ,  G06F9/4403 ,  G06F9/4416 ,  G06F11/1417 ,  G06F21/575 ,  G06F2201/84

Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract translation: 平台控制器，计算机可读存储介质以及与计算设备的初始化相关联的方法。 在实施例中，平台控制器可以包括引导控制器和与引导控制器耦合的一个或多个非易失性存储器模块。 在实施例中，一个或多个非易失性存储器模块可以具有存储在其上的第一指令和第二指令。 第一指令可以在由托管平台控制器的计算设备的处理器执行时引起计算设备的初始化。 该第二指令，当由所述引导控制器执行时，可能会导致引导控制器以监测至少由所述计算设备的所述第一指令的执行的一部分，并且可以产生的所述第一指令的执行的所监控的部分的轨迹。 在实施例中，迹线可以被存储在一个或多个非易失性存储器模块中。 其他实施例可以被描述和/或要求保护。