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    HARDWARE APPARATUSES AND METHODS FOR DISTRIBUTED DURABLE AND ATOMIC TRANSACTIONS IN NON-VOLATILE MEMORY
    32.
    发明申请
    HARDWARE APPARATUSES AND METHODS FOR DISTRIBUTED DURABLE AND ATOMIC TRANSACTIONS IN NON-VOLATILE MEMORY 有权
    非易失性存储器中分布式耐用和原子交易的硬件设备和方法

    公开(公告)号：US20160378672A1

    公开(公告)日：2016-12-29

    申请号：US14752783

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  Sanjay Kumar

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/214 ,  G06F2212/7201

    Abstract: Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus includes a hardware processor, a plurality of hardware memory controllers for each of a plurality of non-volatile data storage devices, and a plurality of staging buffers with a staging buffer for each of the plurality of hardware memory controllers, wherein each of the plurality of hardware memory controllers are to: write data of a data set that is to be written to the plurality of non-volatile data storage devices to their staging buffer, send confirmation to the hardware processor that the data is written to their staging buffer, and write the data from their staging buffer to their non-volatile data storage device on receipt of a commit command.

    Abstract translation: 描述了在非易失性存储器中用于分布式持久和原子事务的硬件装置和方法。 在一个实施例中，硬件设备包括硬件处理器，用于多个非易失性数据存储设备中的每一个的多个硬件存储器控制器，以及多个具有用于多个硬件存储器控制器中的每一个的暂存缓冲器的登台缓冲器 其中，所述多个硬件存储器控制器中的每一个要将要写入所述多个非易失性数据存储装置的数据组的数据写入其暂存缓冲器，向所述硬件处理器发送所述数据被写入的确认 并且在接收到提交命令时将数据从其暂存缓冲区写入其非易失性数据存储设备。

    Method and apparatus for store durability and ordering in a persistent memory architecture
    33.
    发明授权
    Method and apparatus for store durability and ordering in a persistent memory architecture 有权
    用于在持久存储器架构中存储耐久性和排序的方法和装置

    公开(公告)号：US09423959B2

    公开(公告)日：2016-08-23

    申请号：US13931875

    申请日：2013-06-29

    Applicant: Intel Corporation

    Inventor： Subramanya R. Dulloor ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Richard A. Uhlig ,  Robert S. Chappell ,  Joseph Nuzman ,  Kai Cheng ,  Sailesh Kottapalli ,  Yen-Cheng Liu ,  Mohan Kumar ,  Raj K. Ramanujan ,  Glenn J. Hinton

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

    Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

    Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

    PASID based routing extension for scalable IOV systems
    35.
    发明授权
    PASID based routing extension for scalable IOV systems 有权

    公开(公告)号：US12086082B2

    公开(公告)日：2024-09-10

    申请号：US17026516

    申请日：2020-09-21

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

    IPC: G06F13/20 ,  G06F3/06 ,  G06F9/455

    CPC classification number: G06F13/20 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0662 ,  G06F3/0679 ,  G06F9/45558

    Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.

    Techniques for virtual machine transfer and resource management
    37.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11995462B2

    公开(公告)日：2024-05-28

    申请号：US18153177

    申请日：2023-01-11

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

    HIGHLY SCALABLE ACCELERATOR
    40.
    发明申请
    HIGHLY SCALABLE ACCELERATOR 有权

    公开(公告)号：US20210382836A1

    公开(公告)日：2021-12-09

    申请号：US17410063

    申请日：2021-08-24

    Applicant: Intel Corporation

    Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

    IPC: G06F13/364 ,  G06F13/24 ,  G06F9/50

    Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

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