公开(公告)号：US10078453B1

公开(公告)日：2018-09-18

申请号：US15460043

申请日：2017-03-15

Applicant: INTEL CORPORATION

Inventor： Peng Li ,  Sanjeev N. Trika

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F17/30 ,  G06F12/1027

Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.

公开(公告)号：US20180089074A1

公开(公告)日：2018-03-29

申请号：US15279279

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Sanjeev N. Trika

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F2212/1008 ,  G06F2212/1044 ,  G06F2212/202 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: Examples may include techniques to manage key-value storage at a memory or storage device. A key-value command such as a put key-value command is received and data for a key and data for a value included in the put key-value command may be stored in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index is stored in one or more second NVM devices maintained at the memory or storage device. The H2P table or index is utilized to locate and read the data for the key and the data for the value responsive to other key-value commands.

公开(公告)号：US09870462B2

公开(公告)日：2018-01-16

申请号：US14492168

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Jason Cox ,  Anand S. Ramalingam

IPC: G06F21/44 ,  H04L9/32 ,  G06F21/31

CPC classification number: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F2221/2103 ,  H04L9/0894 ,  H04L9/3271

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair.

公开(公告)号：US20180004434A1

公开(公告)日：2018-01-04

申请号：US15198015

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Vinodh Gopal ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.

公开(公告)号：US20170364275A1

公开(公告)日：2017-12-21

申请号：US15186716

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Arun S. Athreya ,  Sanjeev N. Trika

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0634 ,  G06F3/0659 ,  G06F12/0246

Abstract: Technologies for managing end of life behavior of a storage device include an apparatus that includes a memory that includes a plurality of storage cells and a controller to manage read and write operations of the memory. The controller is to determine whether the memory is presently operated in a read-only mode due to a presence of an end of life condition, determine, in response to a determination that the memory is presently operated in the read-only mode and in response to an action of a host, whether to transition the memory to a temporary write mode, and transition, in response to a determination to transition the memory to a temporary write mode, the memory to the temporary write mode. Other embodiments are described and claimed.

公开(公告)号：US20170286294A1

公开(公告)日：2017-10-05

申请号：US15488324

申请日：2017-04-14

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Rowel S. Garcia

IPC: G06F12/0802 ,  G06F12/0871

CPC classification number: G06F12/0802 ,  G06F12/0871 ,  G06F12/0886 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

公开(公告)号：US20170177243A1

公开(公告)日：2017-06-22

申请号：US14975150

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Anand S. Ramalingam

IPC: G06F3/06 ,  G06F11/20 ,  G06F1/26

CPC classification number: G06F3/0619 ,  G06F1/26 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0685 ,  G06F11/1441 ,  G06F11/2015 ,  G06F11/2094 ,  G06F2201/805

Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.

公开(公告)号：US20170123995A1

公开(公告)日：2017-05-04

申请号：US14931410

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： James P. Freyensee ,  Sanjeev N. Trika ,  Bryan E. Veal

IPC: G06F12/10 ,  G06F11/20 ,  G06F11/10

CPC classification number: G06F12/10 ,  G06F11/1076 ,  G06F11/2094 ,  G06F2201/805 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/262 ,  G06F2212/65

Abstract: Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

公开(公告)号：US12112055B2

公开(公告)日：2024-10-08

申请号：US16865566

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Piotr Wysocki ,  Sanjeev N. Trika ,  Gregory B. Tucker ,  Jackson Ellis ,  Jonathan M. Hughes

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/30029

Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.

公开(公告)号：US12061550B2

公开(公告)日：2024-08-13

申请号：US16828700

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Frank T. Hady ,  Sanjeev N. Trika

IPC: G06F8/41 ,  G06F12/0804 ,  G06F12/0815

CPC classification number: G06F12/0815 ,  G06F8/451 ,  G06F12/0804 ,  G06F2212/1016

Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.