公开(公告)号：US20220334736A1

公开(公告)日：2022-10-20

申请号：US17856637

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Hsing-Min Chen ,  Theodros Yigzaw ,  Russell Clapp ,  Saravanan Sethuraman ,  Patricia Mwove Shaffer

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

公开(公告)号：US20210389880A1

公开(公告)日：2021-12-16

申请号：US17412971

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods provide for memory management where an infrastructure processing unit bypasses a central processing unit. Such an infrastructure processing unit determines if incoming packets of memory traffic trigger memory rules stored by the infrastructure processing unit. The incoming packets are routed to the central processing unit in a default mode when the incoming packets do not trigger the memory rules. Conversely, the incoming packets are routed to the infrastructure processing unit and bypass the central processing unit in an inline mode when the incoming packets trigger the memory rules. A memory architecture communicatively coupled to the central processing unit receives a set of atomic transactions from the infrastructure processing unit that bypasses the central processing unit and performs the set of atomic transactions from the infrastructure processing unit.

公开(公告)号：US20210326763A1

公开(公告)日：2021-10-21

申请号：US17359162

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Timothy Verrall

IPC: G06N20/00 ,  H04L9/32 ,  G06K9/62

Abstract: Devices, methods, apparatus, systems, and articles of manufacture to propagate a model in edge architecture are disclosed. An example device includes an interface to access a model received via the edge architecture; at least one memory; instructions in the device; and one or more processors to execute the instructions to: determine a number of attestation responses based on a blockchain associated with the model; determine if the number satisfies a threshold number; initiate an execution of the model in response to verifying that the number satisfies the threshold number; and transmit the model to a plurality of edge appliances in response the number not satisfying the threshold number.

公开(公告)号：US11121940B2

公开(公告)日：2021-09-14

申请号：US15470664

申请日：2017-03-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Andrew Herdrich ,  Edwin Verplanke

IPC: H04L12/851 ,  H04L12/701 ,  H04L12/911 ,  H04L12/24 ,  H04L12/947 ,  H04L5/00

Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.

公开(公告)号：US11099995B2

公开(公告)日：2021-08-24

申请号：US15939118

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Michael Klemm ,  Thomas Willhalm

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F12/0811 ,  G11C13/00 ,  G11C11/00 ,  G11C11/401

Abstract: Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangement of memory. Examples include circuitry for a processor receiving a prefetch request from a core of the processor to prefetch data from the first level to the second level. The prefetch request indicating an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core.

公开(公告)号：US11082525B2

公开(公告)日：2021-08-03

申请号：US16415138

申请日：2019-05-17

Applicant: Intel Corporation

Inventor： Ramanathan Sethuraman ,  Timothy Verrall ,  Ned M. Smith ,  Thomas Willhalm ,  Brinda Ganesh ,  Francesc Guim Bernat ,  Karthik Kumar ,  Evan Custodio ,  Suraj Prabhakaran ,  Ignacio Astilleros Diez ,  Nilesh K. Jain ,  Ravi Iyer ,  Andrew J. Herdrich ,  Alexander Vul ,  Patrick G. Kutch ,  Kevin Bohan ,  Trevor Cooper

IPC: H04L29/08 ,  H04L29/06 ,  H04L9/08

Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.

公开(公告)号：US11029659B2

公开(公告)日：2021-06-08

申请号：US16314401

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Nicolas A. Salhuana ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Narayan Ranganathan

IPC: G06F13/38 ,  G05B19/042 ,  H03K19/17732 ,  G06F8/41 ,  H03K19/17728

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

公开(公告)号：US20210109679A1

公开(公告)日：2021-04-15

申请号：US17127915

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Piotr Wysocki

IPC: G06F3/06 ,  G06N20/00

Abstract: Systems, apparatuses and methods may provide for technology that samples machine learning (ML) data from a local memory in accordance with a specified configuration, wherein the ML data is associated with one or more tasks submitted by one or more processor cores. The technology may also estimate the complexity of the sampled ML data based on one or more thresholds and schedule the task(s) for execution by one or more accelerators based on the complexity and telemetry data associated with a link to the accelerator(s).

公开(公告)号：US10956325B2

公开(公告)日：2021-03-23

申请号：US15375675

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mohan J. Kumar ,  Thomas Willhalm ,  Robert G. Blankenship

IPC: G06F3/06 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0808 ,  G06F13/16 ,  G06F12/128 ,  G06F12/12 ,  G06F12/0868 ,  G06F12/0831

Abstract: Embodiments provide for a processor including a cache a caching agent and a processing node to decode an instruction including at least one operand specifying an address range within a distributed shared memory (DSM) and perform a flush to a first of a plurality of memory devices in the DSM at the specified address range.

公开(公告)号：US10885004B2

公开(公告)日：2021-01-05

申请号：US16012515

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Benjamin Graniello

IPC: G06F12/08 ,  G06F16/22 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804 ,  G06F16/27

Abstract: A group of cache lines in cache may be identified as cache lines not to be flushed to persistent memory until all cache line writes for the group of cache lines have been completed.