公开(公告)号：US20180284868A1

公开(公告)日：2018-10-04

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/32 ,  G06F3/01 ,  G06F11/30 ,  G06F11/07

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170364133A1

公开(公告)日：2017-12-21

申请号：US15611876

申请日：2017-06-02

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US09703352B2

公开(公告)日：2017-07-11

申请号：US14526040

申请日：2014-10-28

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US09489771B2

公开(公告)日：2016-11-08

申请号：US13938192

申请日：2013-07-09

Applicant: Intel Corporation

Inventor： John G. Gierach ,  Travis T. Schluessler

IPC: G06T17/20 ,  G06T15/40

CPC classification number: G06T17/20 ,  G06T15/40

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for separating a group of polygons from a viewpoint of a scene into a dependent subgroup of polygons or a non-dependent subgroup of polygon and spatially sorting the non-dependent subgroup of polygons and the dependent group of polygons separately to form a sorted group of polygons.

Abstract translation: 各种实施例通常涉及一种用于将一组多边形从场景的视点分离成多边形的依赖子组或多个非依赖子组的装置，方法和其他技术，并且对多边形的非依赖子组进行空间分类， 多边形的依赖组分别形成多边形的排序组。

公开(公告)号：US20250053797A1

公开(公告)日：2025-02-13

申请号：US18812822

申请日：2024-08-22

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US20240388439A1

公开(公告)日：2024-11-21

申请号：US18750817

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Travis T. Schluessler

IPC: H04L9/32 ,  G06F9/455 ,  G06F12/14 ,  G06F21/53 ,  G06F21/72

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

公开(公告)号：US20240354043A1

公开(公告)日：2024-10-24

申请号：US18648737

申请日：2024-04-29

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G06F3/14 ,  G06F3/01 ,  G06F3/0484 ,  G09G5/00 ,  G09G5/391

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US12124310B2

公开(公告)日：2024-10-22

申请号：US18339827

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G09G3/06 ,  G06F1/3203 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04W52/02 ,  H04M1/72448

CPC classification number: G06F1/3209 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/0781 ,  G06F11/3062 ,  H04W52/0258 ,  H04M1/72448 ,  Y02D10/00 ,  Y02D30/70

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US12086705B2

公开(公告)日：2024-09-10

申请号：US15858014

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Abhishek Venkatesh ,  Gokce Keskin ,  John Gierach ,  Oguz Elibol ,  Tomer Bar-On ,  Huma Abidi ,  Devan Burke ,  Jaikrishnan Menon ,  Eriko Nurvitadhi ,  Pruthvi Gowda Thorehosur Appajigowda ,  Travis T. Schluessler ,  Dhawal Srivastava ,  Nishant Patel ,  Anil Thomas

IPC: G06N3/063 ,  G06F9/38 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

公开(公告)号：US20240257294A1

公开(公告)日：2024-08-01

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41 ,  G06F2009/45583

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.