公开(公告)号：US11010659B2

公开(公告)日：2021-05-18

申请号：US15495020

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F17/50 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F15/78 ,  G06F15/76 ,  G06F1/3287 ,  G06F1/3293 ,  G06T1/60

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210125581A1

公开(公告)日：2021-04-29

申请号：US17062871

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F12/0875 ,  G06F9/46 ,  G09G5/00

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20210035259A1

公开(公告)日：2021-02-04

申请号：US16930935

申请日：2020-07-16

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Karol A. Szerszen ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker

IPC: G06T1/60 ,  G06F12/0875 ,  G06T1/20

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

公开(公告)号：US10783084B2

公开(公告)日：2020-09-22

申请号：US16702073

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Atlug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0868 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0893 ,  G06F12/126 ,  G06T1/60

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200294301A1

公开(公告)日：2020-09-17

申请号：US16355364

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Arthur Hunter, JR. ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T17/20

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US20200286201A1

公开(公告)日：2020-09-10

申请号：US16297129

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Ben J. Ashbaugh ,  Brandon Fliflet ,  Jeffery S. Boles ,  Srinivasan Embar Raghukrishnan ,  Rahul Kulkarni

IPC: G06T1/20 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

公开(公告)号：US10769083B2

公开(公告)日：2020-09-08

申请号：US16540477

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06F13/16 ,  G06T1/20 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.

公开(公告)号：US20200241622A1

公开(公告)日：2020-07-30

申请号：US16782791

申请日：2020-02-05

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Altug Koker ,  Eric J. Hoekstra ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Kamal Sinha ,  Balaji Vembu ,  Eric J. Asperheim ,  Sanjeev S. Jahagirdar ,  Joydeep Ray

IPC: G06F1/3225 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200098167A1

公开(公告)日：2020-03-26

申请号：US16456645

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Karol A. Szerszen ,  Aleksander Olek Neyman ,  Altug Koker ,  Prasoonkumar Surti ,  Abhishek Appu ,  Joydeep Ray ,  Art Hunter ,  Luis F. Cruz Camacho ,  Akshay R. Chada

IPC: G06T15/40 ,  G06T15/00

Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.

公开(公告)号：US20200082494A1

公开(公告)日：2020-03-12

申请号：US16572161

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.