公开(公告)号：US20200001887A1

公开(公告)日：2020-01-02

申请号：US16021911

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Jagannadha Rapeta

IPC: B60W50/02 ,  H03K3/037 ,  H03K5/24 ,  B60W50/00 ,  G01R19/165 ,  G01R19/12

Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.

公开(公告)号：US20190294125A1

公开(公告)日：2019-09-26

申请号：US16439407

申请日：2019-06-12

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Roger May ,  Prashanth Gadila

IPC: G05B9/02 ,  G06F13/12 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

公开(公告)号：US20190050033A1

公开(公告)日：2019-02-14

申请号：US16155749

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

CPC classification number: G06F1/206 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US20180011528A1

公开(公告)日：2018-01-11

申请号：US14563079

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Jia Jun Lee ,  Asad Azam

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3215 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3296 ,  G06F9/4418 ,  G06F13/4282 ,  Y02D10/151 ,  Y02D10/157

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.