公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20200312950A1

公开(公告)日：2020-10-01

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC: H01L49/02 ,  H01L27/11585 ,  H01L23/522 ,  H01G4/30 ,  H01G4/012

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20240088292A1

公开(公告)日：2024-03-14

申请号：US17940944

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao CHU ,  Feng ZHANG ,  Minwoo JANG ,  Yanbin LUO ,  Chia-Ching LIN ,  Ting-Hsiang HUNG

IPC: H01L29/78 ,  H01L27/11

CPC classification number: H01L29/7846 ,  H01L27/1104 ,  H01L29/7845 ,  H01L29/785

Abstract: Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.

公开(公告)号：US20240006481A1

公开(公告)日：2024-01-04

申请号：US17853547

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Kevin P. O'BRIEN ,  Sudarat LEE ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Chia-Ching LIN ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.

公开(公告)号：US20230411278A1

公开(公告)日：2023-12-21

申请号：US18129264

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Matthew V. METZ ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Aaron J. WELSH

IPC: H01L23/522 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L28/75 ,  H01L28/91 ,  H01L27/0805

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.

公开(公告)号：US20230317783A1

公开(公告)日：2023-10-05

申请号：US17709365

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Carl H. NAYLOR ,  Uygar E. AVCI ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Scott B. CLENDENNING ,  Matthew V. METZ ,  Chia-Ching LIN ,  Sudarat LEE ,  Ashish Verma PENUMATCHA

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L29/78651

Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.

公开(公告)号：US20230102177A1

公开(公告)日：2023-03-30

申请号：US17484981

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ

IPC: H01G4/08 ,  H01L49/02 ,  H01G4/30

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100952A1

公开(公告)日：2023-03-30

申请号：US17485291

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Ashish Verma PENUMATCHA ,  Seung Hoon SUNG ,  Sarah ATANASOV ,  Jack T. KAVALIEROS ,  Matther V. METZ ,  Uygar E. AVCI ,  Rahul RAMAMURTHY ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.