公开(公告)号：US11810980B2

公开(公告)日：2023-11-07

申请号：US16457621

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Martin M. Mitan ,  Leonard C. Pipes

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/768 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/78696 ,  H01L21/76829 ,  H01L27/0688 ,  H01L27/1259 ,  H01L29/6675 ,  H01L29/78618

Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

公开(公告)号：US11784088B2

公开(公告)日：2023-10-10

申请号：US16260632

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang ,  Harish Ganapathy ,  Leonard C. Pipes

IPC: H10B12/00 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H10B12/01 ,  H10B12/20 ,  H10B12/50

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

公开(公告)号：US20220359758A1

公开(公告)日：2022-11-10

申请号：US17308853

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Shailesh Kumar Madisetti ,  Chieh-Jen Ku ,  Wen-Chiang Hong ,  Pei-Hua Wang ,  Cheng Tan ,  Harish Ganapathy ,  Bernhard Sell ,  Lin-Yung Wang

IPC: H01L29/786 ,  H01L29/66

Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.

公开(公告)号：US20210408291A1

公开(公告)日：2021-12-30

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20210408002A1

公开(公告)日：2021-12-30

申请号：US16914152

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Van Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Juan G. Alzate-Vinasco

IPC: H01L27/108

Abstract: An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer.