公开(公告)号：US20200244397A1

公开(公告)日：2020-07-30

申请号：US15761409

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  Joon Teik HOR

IPC: H04L1/00

Abstract: Data of different types are received on a plurality of data lanes of a physical link. Particular data is received on at least a portion of the plurality of data lanes, and a stream signal, corresponding to the particular data, is received on another of the lanes of the physical link, where the particular data is of a particular type different from other data previously sent on the plurality of data lanes. The stream signal includes a code component indicating that the particular data is of the particular type and a parity component for use in identifying whether a bit error is present in the stream signal.

公开(公告)号：US10606785B2

公开(公告)日：2020-03-31

申请号：US16171342

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US10461805B2

公开(公告)日：2019-10-29

申请号：US15761408

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

IPC: H04B3/40 ,  G06F13/20 ,  H04L25/03

Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

公开(公告)号：US20190227972A1

公开(公告)日：2019-07-25

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20190065426A1

公开(公告)日：2019-02-28

申请号：US16171342

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US09952643B2

公开(公告)日：2018-04-24

申请号：US14986573

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Lily Pao Looi

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F9/4418 ,  G06F13/4265 ,  G06F13/4282 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/44

Abstract: Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170294906A1

公开(公告)日：2017-10-12

申请号：US15632836

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC: H03K5/26 ,  G06F1/32 ,  G06F13/42 ,  H03L9/00 ,  G01R31/04

CPC classification number: H03K5/26 ,  G01R31/041 ,  G06F1/3296 ,  G06F13/4291 ,  H03K5/131 ,  H03L9/00

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

公开(公告)号：US09753529B2

公开(公告)日：2017-09-05

申请号：US15158271

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G08C17/00 ,  G06F1/32 ,  H04W52/02 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

公开(公告)号：US09600433B2

公开(公告)日：2017-03-21

申请号：US14261934

申请日：2014-04-25

Applicant: INTEL CORPORATION

Inventor： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

公开(公告)号：US20160285624A1

公开(公告)日：2016-09-29

申请号：US14669743

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer

IPC: H04L9/06

CPC classification number: H04B3/46 ,  H04B3/32 ,  H04B3/487

Abstract: In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others. The interconnect is permitted to move from “CENTERING” to “LOOPBACK” via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage Vref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit.

Abstract translation: 在一个示例中，线性反馈移位寄存器（LFSR）向用于训练，测试和加扰目的的互连提供伪随机比特序列（PRBS）。 互连可以包括状态机，其中包括LOOPBACK，CENTERING，RECENTERING和ACTIVE状态等状态。 互连允许通过边带信号从“CENTERING”移动到“LOOPBACK”。 在LOOPBACK，CENTERING和RECENTERING中，PRBS用于训练和测试目的，用于对互连进行电性能和测试，并定位参考电压Vref的中点。 使用一个公共输出位计算每个通道提供一个独特的，不相关的PRBS。