公开(公告)号：US20180189104A1

公开(公告)日：2018-07-05

申请号：US15396529

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh Sankaran ,  Stephen Van Doren

IPC: G06F9/50 ,  G06F9/455

Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.

公开(公告)号：US20180129619A1

公开(公告)日：2018-05-10

申请号：US15865430

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Gideon Gerzon ,  Richard Uhlig ,  Sergiu Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC: G06F13/26 ,  G06F13/24 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F13/26 ,  G06F9/30076 ,  G06F9/45541 ,  G06F9/45558 ,  G06F13/24 ,  G06F2009/45579 ,  G06F2213/0058

Abstract: Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

公开(公告)号：US12271616B2

公开(公告)日：2025-04-08

申请号：US17348586

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  David Koufaty ,  Rajesh Sankaran ,  Vedvyas Shanbhogue

IPC: G06F3/06 ,  G06F13/28

Abstract: An embodiment of an integrated circuit comprises circuitry to share page tables associated with a page between a processor memory management unit (MMU) and an input/output memory management unit (IOMMU), store a page table entry in the memory associated with the page, and separately control access to the page from a processor and from a direct memory access (DMA) request based on one or more fields of the stored page table entry. Other embodiments are disclosed and claimed.

公开(公告)号：US12229581B2

公开(公告)日：2025-02-18

申请号：US18239489

申请日：2023-08-29

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Bret Toll ,  William Rash ,  Subramaniam Maiyuran ,  Gang Chen ,  Varghese George

IPC: G06F9/455 ,  G06F12/1009 ,  G06T1/20

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

公开(公告)号：US12086082B2

公开(公告)日：2024-09-10

申请号：US17026516

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

IPC: G06F13/20 ,  G06F3/06 ,  G06F9/455

CPC classification number: G06F13/20 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0662 ,  G06F3/0679 ,  G06F9/45558

Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.

公开(公告)号：US11921646B2

公开(公告)日：2024-03-05

申请号：US17842094

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： David Koufaty ,  Rajesh Sankaran ,  Anna Trikalinou ,  Rupin Vakharwala

IPC: G06F12/14 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/1483 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2212/305 ,  G06F2212/6028 ,  G06F2213/0026

Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.

公开(公告)号：US20230205562A1

公开(公告)日：2023-06-29

申请号：US17560251

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Vedvyas Shanbhogue ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya ,  Eric Geisler ,  Ravi Sahita

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45587 ,  G06F2009/45583 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Systems, methods, and apparatuses for implementing input/output extensions for trust domains are described. In one example, a hardware processor includes a hardware processor core comprising a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, and input/output memory management unit (IOMMU) circuitry coupled between the hardware processor core and an input/output device, wherein the IOMMU circuitry is to, for a request from the input/output device for a direct memory access of a protected memory of a trust domain, allow the direct memory access in response to a field in the request being set to indicate the input/output device is in a trusted computing base of the trust domain.

公开(公告)号：US20230142399A1

公开(公告)日：2023-05-11

申请号：US17521518

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran

IPC: G06F9/48 ,  G06F9/32 ,  G06F13/24

CPC classification number: G06F9/4812 ,  G06F9/327 ,  G06F13/24

Abstract: An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

公开(公告)号：US20230099517A1

公开(公告)日：2023-03-30

申请号：US17561452

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Asit Mallick ,  Rajesh Sankaran ,  Hisham Shafi ,  Vedvyas Shanbhogue ,  Vivekananthan Sanjeepan ,  Jason Brandt

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/30

Abstract: Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

公开(公告)号：US20220405212A1

公开(公告)日：2022-12-22

申请号：US17352631

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  David Koufaty

IPC: G06F12/14 ,  G06F12/1009

Abstract: An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.