公开(公告)号：US20200043917A1

公开(公告)日：2020-02-06

申请号：US16489847

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/778

Abstract: Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device.

公开(公告)号：US10475706B2

公开(公告)日：2019-11-12

申请号：US15430348

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

公开(公告)号：US20190305182A1

公开(公告)日：2019-10-03

申请号：US15940440

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L33/20 ,  H01L33/32 ,  H01L33/00 ,  H01L33/10 ,  H01L33/08

Abstract: Micro LED displays offer brighter screens and wider color gamuts than that achievable using traditional LED or OLED displays. Various embodiments are directed to LED and micro LED structures having substrates comprising a metal and oxygen, such as gallium and oxygen, and methods of forming the same. An integrated circuit (IC) structure can include a substrate comprising a metal and oxygen and a core over the substrate. The core can include a group III semiconductor material and nitrogen, and the core can be doped with n-type or p-type dopants. An active layer comprising indium can be provide on a surface of the core. The indium concentration can be adjusted to tune a peak emission wavelength of the IC structure. The IC structure can include a cladding on a surface of the active layer. The cladding can be doped with dopants of opposite type than those used to dope the core.

公开(公告)号：US10411067B2

公开(公告)日：2019-09-10

申请号：US15777511

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L21/8238 ,  H01L27/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/20 ,  H03H9/05 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L27/092 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L41/187 ,  H01L41/314 ,  H03H3/02 ,  H03H9/17 ,  H03H9/56 ,  H01L29/08 ,  H01L21/762

Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate. In a more general sense, the techniques can be used for SoC integration of an RF frontend having diverse III-N componentry on a single substrate, in accordance with some embodiments.

公开(公告)号：US10347834B2

公开(公告)日：2019-07-09

申请号：US15928220

申请日：2018-03-22

Applicant: INTEL CORPORATION

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke

IPC: H01L49/00 ,  G02B6/12 ,  G06N10/00 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y20/00

Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

公开(公告)号：US20190044066A1

公开(公告)日：2019-02-07

申请号：US15928220

申请日：2018-03-22

Applicant: INTEL CORPORATION

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke

IPC: H01L49/00 ,  G02B6/12 ,  G06N99/00

CPC classification number: H01L49/006 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G02B6/12004 ,  G02B2006/12078 ,  G02B2006/12142 ,  G06N10/00 ,  Y10S977/814 ,  Y10S977/933

Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

公开(公告)号：US20180350911A1

公开(公告)日：2018-12-06

申请号：US16041657

申请日：2018-07-20

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

公开(公告)号：US20180331224A1

公开(公告)日：2018-11-15

申请号：US16040505

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz Gardner ,  Ravi Pillarisetty

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L21/306 ,  H01L21/762 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20 ,  H01L29/06 ,  H01L29/34

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US10096683B2

公开(公告)日：2018-10-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/20 ,  H01L29/80 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/06 ,  H01L29/201 ,  H01L29/778 ,  H01L21/283 ,  H01L29/423

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US09865684B2

公开(公告)日：2018-01-09

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/308

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.