公开(公告)号：US20190251264A1

公开(公告)日：2019-08-15

申请号：US16392863

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ron Story ,  Mahesh Natu

IPC: G06F21/57 ,  G06F9/455 ,  G06F9/4401 ,  G06F9/448

CPC classification number: G06F21/572 ,  G06F9/4411 ,  G06F9/449 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: Technologies for secure native code invocation include a computing device having an operating system and a firmware environment. The operating system executes a firmware method in an operating system context using a virtual machine. In response to invoking the firmware method, the operating system invokes a callback to a bridge driver in the operating system context. In response to the callback, the bridge driver invokes a firmware runtime service in the operating system context. The firmware environment executes a native code handler in the operating system context in response to invoking the firmware runtime service. The native code handler may be executed in a de-privileged container. The firmware method may process results data stored in a firmware mailbox by the native code handler, which may include accessing a hardware resource using a firmware operation region. Other embodiments are described and claimed.

公开(公告)号：US20190065211A1

公开(公告)日：2019-02-28

申请号：US16050240

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F9/4401 ,  G06F11/30 ,  G06F17/30 ,  G06F1/26 ,  G06F1/28 ,  G06F11/36 ,  G06F1/32 ,  G06F9/22 ,  G06F9/445 ,  G06F9/44 ,  G06F11/34 ,  G06F1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US20180188966A1

公开(公告)日：2018-07-05

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2094

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

公开(公告)号：US20180004595A1

公开(公告)日：2018-01-04

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/0875 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/0721

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20170286333A1

公开(公告)日：2017-10-05

申请号：US15085734

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

公开(公告)号：US09645829B2

公开(公告)日：2017-05-09

申请号：US14319361

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Adam J. Brooks ,  George Vergis

IPC: G06F11/14 ,  G06F9/44 ,  G06F11/20

CPC classification number: G06F9/4401 ,  G06F11/1441 ,  G06F11/2015

Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.

公开(公告)号：US12223308B2

公开(公告)日：2025-02-11

申请号：US18040147

申请日：2020-08-25

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Brett Peng Wang ,  Ashok Raj ,  Murugasamy Nachimuthu

IPC: G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F9/4401

Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

公开(公告)号：US12130924B2

公开(公告)日：2024-10-29

申请号：US17134329

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Jiewen Yao ,  Murugasamy K Nachimuthu ,  Ruixia Li ,  Siyuan Fu

IPC: G06F21/57 ,  G06F21/31 ,  G06F21/79

CPC classification number: G06F21/572 ,  G06F21/31 ,  G06F21/575 ,  G06F21/79

Abstract: Methods and apparatus for seamless SMM (System Management Mode) global driver update base on SMM Root-of-Trust. Mechanisms are provided to load and replace SMM drivers at runtime in a secure manner, without requiring an SMM firmware update and platform reset. SMM code is executed by BIOS during boot in a hidden area of memory called SMRAM space. Seamless update using an SMM Global Driver Update provides a method to load and replace all SMM drivers (including SMM infrastructure) on an already shipped platform production for purposes such as bug fixes. The principles and teachings may also be applied to update other types of secure execution mode code in addition to SMM code.

公开(公告)号：US11900115B2

公开(公告)日：2024-02-13

申请号：US18126920

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/30098 ,  G06F9/4812 ,  G06F9/5005 ,  G06F15/80

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US20230305834A1

公开(公告)日：2023-09-28

申请号：US18040147

申请日：2020-08-25

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Brett Peng Wang ,  Ashok Raj ,  Murugasamy Nachimuthu

IPC: G06F8/65 ,  G06F9/4401

CPC classification number: G06F8/65 ,  G06F9/4418

Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.