公开(公告)号：US20190355091A1

公开(公告)日：2019-11-21

申请号：US15982680

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T3/40 ,  G06T1/20

Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.

公开(公告)号：US12057090B2

公开(公告)日：2024-08-06

申请号：US17072694

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Thomas Petersen ,  Charles Moidel ,  Gary Smith ,  Zhe Wang ,  Rafal Rudnicki

IPC: G09G5/18 ,  G06T1/60

CPC classification number: G09G5/18 ,  G06T1/60 ,  G09G2354/00 ,  G09G2360/06

Abstract: Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.

公开(公告)号：US20240231851A1

公开(公告)日：2024-07-11

申请号：US18582311

申请日：2024-02-20

Applicant: Intel Corporation

Inventor： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

IPC: G06F9/448 ,  G06F16/215 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/4488 ,  G06F16/215 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

公开(公告)号：US11769288B2

公开(公告)日：2023-09-26

申请号：US17868618

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US11763515B2

公开(公告)日：2023-09-19

申请号：US17206584

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC: G06T15/04 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T15/04 ,  G06T15/005 ,  G06T15/80

Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.

公开(公告)号：US11443406B2

公开(公告)日：2022-09-13

申请号：US17323818

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06N20/00 ,  G06N3/08 ,  G06T1/60 ,  G06F9/46

Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.

公开(公告)号：US20220122566A1

公开(公告)日：2022-04-21

申请号：US17072694

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Thomas Petersen ,  Charles Moidel ,  Gary Smith ,  Zhe Wang ,  Rafal Rudnicki

IPC: G09G5/18 ,  G06T1/60

Abstract: Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.

公开(公告)号：US20220059054A1

公开(公告)日：2022-02-24

申请号：US17461228

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US11107444B2

公开(公告)日：2021-08-31

申请号：US16723337

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G09G5/377 ,  G06F3/14

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US20210241418A1

公开(公告)日：2021-08-05

申请号：US17234039

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.