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公开(公告)号：BR9305727A
公开(公告)日：1997-11-18
申请号：BR9305727
申请日：1993-10-26
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , DOSS WILLIAM K , ROBBINS KAREN E , YEDINAK MARK A , HAMILLON R LEE JR
Abstract: A method and apparatus for preserving the sequential relationship of a plurality of data packets 310 generated by separate source devices 14 and ordered as a data stream 300, despite transmission over radio channels which introduce ordering errors comprises method steps and apparatus structure for identifying at a first terminal, data packets from within the data stream as a function of source, generating data packet sequence information for identified data packets, storing values corresponding to data packet sequence numbers as a function of source and transmitting data packets, source device identity and packet sequence information to a second terminal having first terminal source device and data packet sequence information. Upon receipt of a first terminal transmission, the second terminal retrieves from second terminal memory, first terminal data packet sequence information and compares the stored data packet sequence information with received data packet sequence information. As a function of the comparison, received data packets are forwarded to an appropriate application for further processing when sequence information sequence numbers compare and stored in an order determined by the sequence information when the sequence numbers do not compare.
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公开(公告)号：BR9205487A
公开(公告)日：1994-06-21
申请号：BR9205487
申请日：1992-01-27
Applicant: MOTOROLA INC
Inventor： KACZMARCZYK JOHN M , BUCHHOLZ DALE R , FREEBURG THOMAS A , O'BRIEN RITA , WHITE RICHARD E
Abstract: A common communication controller (17) is linked to a plurality of peripheral devices (28) by a network interface bus (26). Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller (17) and peripherals (28).
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公开(公告)号：MX9307097A
公开(公告)日：1994-05-31
申请号：MX9307097
申请日：1993-11-12
Applicant: MOTOROLA INC
Inventor： YEDINAK MARK A , HAMILTON R LEE JR , BUCHHOLZ DALE R , DOSS WILLIAM K , ROBBINS KAREN E
Abstract: A method and apparatus for preserving the sequential relationship of a plurality of data packets 310 generated by separate source devices 14 and ordered as a data stream 300, despite transmission over radio channels which introduce ordering errors comprises method steps and apparatus structure for identifying at a first terminal, data packets from within the data stream as a function of source, generating data packet sequence information for identified data packets, storing values corresponding to data packet sequence numbers as a function of source and transmitting data packets, source device identity and packet sequence information to a second terminal having first terminal source device and data packet sequence information. Upon receipt of a first terminal transmission, the second terminal retrieves from second terminal memory, first terminal data packet sequence information and compares the stored data packet sequence information with received data packet sequence information. As a function of the comparison, received data packets are forwarded to an appropriate application for further processing when sequence information sequence numbers compare and stored in an order determined by the sequence information when the sequence numbers do not compare.
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公开(公告)号：MX172698B
公开(公告)日：1994-01-07
申请号：MX2223790
申请日：1990-09-05
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：NZ236320A
公开(公告)日：1992-10-28
申请号：NZ23632090
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , KACZMARCZYK JOHN M , BUCHHOLZ DALE R , WHITE RICHARD E , CHANG HUNGKUN J , NOLAN MICHAEL P
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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Patent Agency Ranking
公开(公告)号：BR9105220A
公开(公告)日：1992-07-21
申请号：BR9105220
申请日：1991-12-02
Applicant: MOTOROLA INC
Inventor： BUCHHOLZ DALE R , CHANG HUNGKUN J , DOSS WILLIAM K , WOSSELMAN BRIAN J
Abstract: An RF communication system contains a control module (22) which communicates with a plurality of user modules (20) that are each connected to at least one user device (24). The system provides a means for packet communications in which traditional destination addressed packets (34) are communicated to the specified destination point (24) or user module (20) while also permitting information (52) intended for a plurality of user modules (20) to be broadcast simultaneously to all user modules (20) using a broadcast protocoal (46). The probability of each UM (20) receiving the broadcast packet (46) is enhanced by the transmission by the control module (22) of each broadcast packet (46) over at least several of its directional antennas (A1-A6) and preferably repeated over each antenna (A1-A6) a number of times (R). Packets of data (34) which are longer than a predetermined number of bytes (L) are broken into packet fragments (46).
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公开(公告)号：AU624745B2
公开(公告)日：1992-06-18
申请号：AU6524790
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：HUT58173A
公开(公告)日：1992-01-28
申请号：HU625890
申请日：1990-09-28
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：BR9006928A
公开(公告)日：1991-10-08
申请号：BR9006928
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：AU6524790A
公开(公告)日：1991-04-28
申请号：AU6524790
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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