公开(公告)号：EP0587792A1

公开(公告)日：1994-03-23

申请号：EP92913963.0

申请日：1992-06-02

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  SHARP, Ronald, E. ,  YESTER, Francis, R.

IPC: H04B1 ,  H04B7 ,  H04L1 ,  H04M1 ,  H04W52

CPC classification number: H04B1/1027 ,  H04B1/1615 ,  H04L1/20 ,  H04W52/0238 ,  Y02D70/40

Abstract: A communication device 200 capable of operating in a communication system 100 having a control system which generates information signals with redundant information is disclosed. The communication device comprises: a receiver 214 for receiving the information signals; a circuit which can determine the signal quality of the received information signals 234; and a controller 226 which decodes the received information signals, and further compares the signal quality of the information signals with a predetermined value, and decides if the received signal quality is at least equal to the predetermined value in order to only decode a portion of the information signal. Upon the communication device decoding a portion of the information signal, the communication device 200 is placed in a battery saving mode in order to conserve battery life.

Abstract translation: 公开了能够在具有生成具有冗余信息的信息信号的控制系统的通信系统100中进行操作的通信装置200。 通信设备包括：接收器214，用于接收信息信号; 可以确定接收到的信息信号234的信号质量的电路; 以及对接收到的信息信号进行解码的控制器226，并且将信息信号的信号质量与预定值进行比较，并且确定接收到的信号质量是否至少等于预定值，以便仅解码部分 信息信号。 在通信设备对信息信号的一部分进行解码时，通信设备200被置于电池节电模式以便节省电池寿命。

公开(公告)号：EP0565555A1

公开(公告)日：1993-10-20

申请号：EP92901534.0

申请日：1991-11-21

Applicant: MOTOROLA, INC.

Inventor： BURNS, Arthur, G. ,  STENGEL, Robert, E.

IPC: H02J7 ,  H02J9

CPC classification number: H02J7/34 ,  H02J7/0011 ,  H02J9/061 ,  Y10S320/24

Abstract: Une batterie rechargeable (10) comprend au moins un élément (7) présentant une borne positive et une borne négative. Un circuit de régulation à commutation (9), couplé à l'élément (7), est utilisé de manière sélective pour réguler la puissance de sortie de la batterie (28) et la charge (12) de la batterie.

公开(公告)号：WO2008042550A2

公开(公告)日：2008-04-10

申请号：PCT/US2007/077819

申请日：2007-09-07

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F1/565 ,  H03F3/26 ,  H03F3/602 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/45394 ,  H03F2203/45731

Abstract: An apparatus and method for eliminating unwanted signal power dissipation in balanced amplifier circuits and for prohibiting unwanted signal power from appearing at the balanced amplifier load is presented. Load impedances to the amplifier power output transistors are maintained very low at unwanted frequencies, and are at an operational impedance level at the fundamental frequency. An impedance network control concept is presented, which may be either manually or automatically implemented.

Abstract translation: 提出了用于消除平衡放大器电路中不需要的信号功率耗散并且用于禁止在平衡放大器负载处出现不想要的信号功率的装置和方法。 放大器功率输出晶体管的负载阻抗在不需要的频率下保持非常低，并且在基频处于工作阻抗级。 提出了阻抗网络控制概念，可以手动或自动实现。

公开(公告)号：WO2007143255A3

公开(公告)日：2007-12-13

申请号：PCT/US2007/065030

申请日：2007-03-27

Applicant: MOTOROLA, INC. ,  STENGEL, Robert, E.

Inventor： STENGEL, Robert, E.

IPC: G06F1/02

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

公开(公告)号：WO2006121629A3

公开(公告)日：2006-11-16

申请号：PCT/US2006/016048

申请日：2006-04-27

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

IPC: H03F3/60

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

公开(公告)号：WO2006039099A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/032667

申请日：2005-09-14

Applicant: MOTOROLA, INC. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H03B21/00

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).

Abstract translation: 一种直接数字合成器（DDS）（300），其使用用于减少数字 - 时间转换器（DTC）中的杂散发射的系统（317）。 DDS（300）包括一个或多个抖动源（307）和随机存取存储器（RAM）（305）。 RAM（305）通过使用与抖动源（307）组合的查找表的输出来利用查找表来存储延迟误差值，以补偿DTC（317）中的不相等的单位延迟值。

公开(公告)号：WO2004105229A1

公开(公告)日：2004-12-02

申请号：PCT/US2004/015469

申请日：2004-05-18

Applicant: MOTOROLA, INC., a corporation of the State of Delaware ,  TOMERLIN, Andrew ,  STENGEL, Robert, E.

Inventor： TOMERLIN, Andrew ,  STENGEL, Robert, E.

IPC: H03B19/00

CPC classification number: H03L7/087 ,  H03K3/84 ,  H03K5/00006 ,  H03K5/1504 ,  H03L7/0812 ,  H04B1/707 ,  H04B2201/70707

Abstract: A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, …, 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Abstract translation: 与本发明的某些实施例一致的频率扩展电路具有具有多个抽头的第一延迟线（108）。 延迟线在时钟速率为FREF的输入处接收参考时钟。 第二延迟线（104,150）还在输入处接收参考时钟。 逻辑电路（130,134，...，138,140）组合来自第一延迟线（108）的延迟线抽头的信号与来自第二和/或第一延迟线（104）的延迟线抽头的信号， 以产生具有FREF * 2N的组合时钟速率的时钟脉冲的集合。 使用延迟锁定环路，至少一个延迟线可以锁定到参考时钟。 时钟脉冲可以与种子寄存器（204）内容逻辑地组合以产生递归序列或用于卷积编码的数据，或者与用于CDMA收发器中的相关的导频数据相结合。

公开(公告)号：WO2003058861A1

公开(公告)日：2003-07-17

申请号：PCT/US2002/039321

申请日：2002-12-10

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L. ,  STENGEL, Robert, E. ,  JUAN, Jui-Kuo

IPC: H04J1/20

CPC classification number: H03L7/22 ,  H03L7/0812 ,  H03L7/16

Abstract: A D/P converter (100) includes a controller (102) for controlling a plurality of D/P blocks (104, 106, 108). Each of the individual D/P blocks (104, 106, 108) provides an output signal (132, 134, 136) which is combined by a combiner (110) to produce an output signal (112). The D/P converter (100) produces outputs at a rate up to one per reference clock cycle. This allows for minimization of power consumption of the D/P converter (100) and/or improved frequency range for a synthesizer or other device utilizing the D/P converter (100).

Abstract translation: D / P转换器（100）包括用于控制多个D / P块（104,106,108）的控制器（102）。 各个D / P块（104,106,108）中的每一个提供由组合器（110）组合以产生输出信号（112）的输出信号（132,134,136）。 D / P转换器（100）以每个参考时钟周期多达一个速率产生输出。 这允许使用D / P转换器（100）的合成器或其他设备的D / P转换器（100）的功耗最小化和/或改善的频率范围。

公开(公告)号：WO2003052992A3

公开(公告)日：2003-06-26

申请号：PCT/US2002/039319

申请日：2002-12-10

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  OLSON, Scott, A.

IPC: H03F1/00

Abstract: A feedforward amplifier and notch filter (300) according to the present invention uses a direct coupling of an amplifier stage (370) with the amplifier's load (RL). The main amplifier (304) is coupled through a transmission line (308) to the load (ZL). This direct coupled amplifier stage (370) is driven by an signal that induces a very low impedance in parallel with the load at the receive frequency, but appears as an open circuit at the desired frequencies so that the desired signal from the main amplifier (304) is virtually unaffected while output components at the receive frequency are cancelled.

公开(公告)号：WO2003017373A3

公开(公告)日：2003-02-27

申请号：PCT/US2002/025342

申请日：2002-08-09

Applicant: MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE

Inventor： HIGGINS, JR., Robert, J. ,  STENGEL, Robert, E.

IPC: H01L27/20

Abstract: High quality layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22, 2615) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24,2610) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating bufferlayer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The use of monocrystalline piezoelectric material as an overlying layer (2605) is disclosed to facilitate the fabrication of on-chip high frequency communications devices such as microwave SAW devices with direct interface to high speed semiconductor devices in the integrated circuit.