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公开(公告)号：US20190267095A1
公开(公告)日：2019-08-29
申请号：US16411622
申请日：2019-05-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu
Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.
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公开(公告)号：US20190066787A1
公开(公告)日：2019-02-28
申请号：US15569854
申请日：2017-08-28
Applicant: MICRON TECHNOLOGY, INC.
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C16/349
Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.
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公开(公告)号：US10153047B2
公开(公告)日：2018-12-11
申请号：US14935744
申请日：2015-11-09
Applicant: Micron Technology, Inc.
Inventor： Jun Xu
Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
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公开(公告)号：US20140177335A1
公开(公告)日：2014-06-26
申请号：US14122577
申请日：2012-03-13
Applicant: MICRON TECHNOLOGY ,INC.
Inventor： Jun Xu
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/56 , G11C11/5642
Abstract: The present disclosure includes apparatuses and methods for nonconsecutive sensing of multilevel memory cells. A number of methods include sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
Abstract translation: 本公开包括用于多层存储器单元的非连续感测的装置和方法。 许多方法包括使用感测信号来感测来自多级存储器单元（MLC）的信息单元。 信息单元可以对应于一页信息。 MLC可以存储对应于多页信息的多个信息单元。 感测信号可以从第一感测幅度变化到第二感测幅度，并且从第二感测幅度变为第三感测量级。 第二检测幅度可以是与第一感测幅度非连续的，和/或第三感测幅度可以相对于对应于MLC的多个电荷存储状态的多个感测量级从第二感测幅度不连续。
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公开(公告)号：US20240071531A1
公开(公告)日：2024-02-29
申请号：US18239193
申请日：2023-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tomoko Ogura Iwasaki , Hong-Yan Chen , Pamela Castalino , Priya Vemparala Guruswamy , Jun Xu , Gianluca Nicosia , Ji-Hye Gale Shin
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/102 , G11C16/12
Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.
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Patent Agency Ranking
公开(公告)号：US11862257B2
公开(公告)日：2024-01-02
申请号：US17989168
申请日：2022-11-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Violante Moschiano , Erwin E. Yu
CPC classification number: G11C16/3454 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3404
Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
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公开(公告)号：US11862255B2
公开(公告)日：2024-01-02
申请号：US17666955
申请日：2022-02-08
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Theodore T. Pekny
IPC: G11C16/34
CPC classification number: G11C16/3431 , G11C16/349
Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.
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公开(公告)号：US11615846B2
公开(公告)日：2023-03-28
申请号：US17832117
申请日：2022-06-03
Applicant: Micron Technology, Inc.
Inventor： Huanyou Zhan , Massimo Rossini , Jun Xu
Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.
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公开(公告)号：US20230017995A1
公开(公告)日：2023-01-19
申请号：US17666955
申请日：2022-02-08
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Theodore T. Pekny
IPC: G06F3/06
Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.
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公开(公告)号：US20220404408A1
公开(公告)日：2022-12-22
申请号：US17894227
申请日：2022-08-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dan Xu , Jun Xu , Erwin E. Yu
Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.
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