Solar cell
    31.
    发明授权
    Solar cell 有权
    太阳能电池

    公开(公告)号:US08952244B2

    公开(公告)日:2015-02-10

    申请号:US13089321

    申请日:2011-04-19

    Abstract: A solar cell includes a semiconductor substrate, a doping layer, a quantum well layer, a first passivation layer, a second passivation layer, a first electrode and a second electrode. The semiconductor substrate has a front surface and a back surface, and the front surface of the semiconductor substrate includes nano-rods. The doping layer covers the surface of the nano-rods. The electrode layers cover the doping layer. The quantum well layer having at least one first doping region and at least one second doping region is disposed on the semiconductor substrate. The quantum well layer includes polycrystalline silicon germanium (Si1-xGex). The first passivation layer and the second passivation layer cover the first and the second doping regions of the quantum well layer, respectively. The first electrode and the second electrode are electrically connected to the first doping region and the second doping region of the quantum well layer, respectively.

    Abstract translation: 太阳能电池包括半导体衬底,掺杂层,量子阱层,第一钝化层,第二钝化层,第一电极和第二电极。 半导体衬底具有前表面和后表面,并且半导体衬底的前表面包括纳米棒。 掺杂层覆盖纳米棒的表面。 电极层覆盖掺杂层。 具有至少一个第一掺杂区域和至少一个第二掺杂区域的量子阱层设置在半导体衬底上。 量子阱层包括多晶硅锗(Si1-xGex)。 第一钝化层和第二钝化层分别覆盖量子阱层的第一和第二掺杂区域。 第一电极和第二电极分别电连接到量子阱层的第一掺杂区域和第二掺杂区域。

    ELECTRONIC MODULE, LIGHTING DEVICE AND MANUFACTURING METHOD OF THE ELECTRONIC MODULE
    32.
    发明申请
    ELECTRONIC MODULE, LIGHTING DEVICE AND MANUFACTURING METHOD OF THE ELECTRONIC MODULE 审中-公开
    电子模块,照明设备和电子模块的制造方法

    公开(公告)号:US20140362590A1

    公开(公告)日:2014-12-11

    申请号:US14238204

    申请日:2012-08-10

    Abstract: An electronic module to be mounted on a mounting surface may include: a circuit board provided with a heat source, wherein a thermal via is formed through the circuit board and is in thermal contact with the heat source; and a potting material packaging the circuit board at least at the other side opposite to one side of heat source, wherein the potting material has a recess formed in at least part of an area corresponding to the thermal via at the other side of the circuit board and a thermal conductive material, which is thermal-conductively connected to the mounting surface, is filled in the recess.

    Abstract translation: 安装在安装表面上的电子模块可以包括:设置有热源的电路板,其中热通孔通过电路板形成并与热源热接触; 以及灌封材料至少在与热源一侧相对的另一侧封装所述电路板,其中所述灌封材料具有形成在与所述电路板的另一侧上的热通孔对应的区域的至少一部分中的凹部 并且导热连接到安装表面的导热材料填充在凹部中。

    Electrical parameter detection device for peripheral component interconnect devices
    33.
    发明授权
    Electrical parameter detection device for peripheral component interconnect devices 有权
    用于外围组件互连设备的电气参数检测装置

    公开(公告)号:US08872521B2

    公开(公告)日:2014-10-28

    申请号:US13424394

    申请日:2012-03-20

    CPC classification number: G06F11/221

    Abstract: An electrical parameter detection device is configured for detecting electrical parameters of a peripheral component interconnect (PCI) connector including a plurality of power pins. The electrical parameter detection device includes a processor module, a first detection module, and a second detection module. The processor module continuously detects voltage values of electric potentials provided by each of the power pins of the PCI connector using the first detection module, and determines time sequences of the electric potentials according to the voltage values of the electric potentials. Furthermore, the processor module detects the amount of power provided by each of the power pins of the PCI connector using the second detection module.

    Abstract translation: 电参数检测装置被配置为检测包括多个电源引脚的外围组件互连(PCI)连接器的电参数。 电参数检测装置包括处理器模块,第一检测模块和第二检测模块。 处理器模块使用第一检测模块连续地检测由PCI连接器的每个电源引脚提供的电位的电压值,并且根据电位的电压值确定电位的时间序列。 此外,处理器模块使用第二检测模块检测由PCI连接器的每个电源引脚提供的电力量。

    Overcurrent protection device
    34.
    发明授权
    Overcurrent protection device 有权
    过电流保护装置

    公开(公告)号:US08854782B2

    公开(公告)日:2014-10-07

    申请号:US13086405

    申请日:2011-04-14

    CPC classification number: H02H3/087 G06F1/28

    Abstract: An overcurrent protection device includes a power input terminal, a power output terminal, a first signal terminal, a second signal terminal, a testing circuit, and a switch element. The power input terminal and the first signal terminal are connected to a power supply. The power output terminal and the second signal terminal are connected to a computer motherboard. If the first and second terminals are disconnected from each other when the computer motherboard works, the power supply stops working. The testing circuit includes a fixed resistor and a control chip parallel connected between the power input and output terminal. The control chip stores a predetermined voltage threshold, and detects voltage between the two terminals of the fixed resistor, and compares the measured voltage with the predetermined voltage threshold. The switch element disconnects the first and second signal terminals when the measured voltage is greater than the predetermined voltage threshold.

    Abstract translation: 过电流保护装置包括电源输入端子,电力输出端子,第一信号端子,第二信号端子,测试电路和开关元件。 电源输入端子和第一信号端子连接到电源。 电源输出端子和第二信号端子连接到计算机主板。 当计算机主板工作时,如果第一和第二端子彼此断开,则电源停止工作。 测试电路包括一个固定电阻和一个并联在电源输入和输出端之间的控制芯片。 控制芯片存储预定电压阈值,并且检测固定电阻器的两个端子之间的电压,并将测量的电压与预定电压阈值进行比较。 当测量的电压大于预定电压阈值时,开关元件断开第一和第二信号端子。

    Detection device
    35.
    发明授权
    Detection device 失效
    检测装置

    公开(公告)号:US08700817B2

    公开(公告)日:2014-04-15

    申请号:US13329224

    申请日:2011-12-17

    CPC classification number: G06F1/28

    Abstract: A detection device to detect a power serving time of a super capacitor for a power-disconnected storage card and an amount of the data packets capable of being stored during the detected serving time is provided. The power-disconnected storage card includes a memory. The detection device includes a power supply unit, the super capacitor, a controller, a storage unit, and a detection unit. The storage unit stores the data packets. The detection unit includes a charge notification module, a data notification module and a time module. The charge notification module generates a first notification signal to the time module. The data notification module generates a second notification signal to the time module when the storage unit transmits the data packet to the memory. The time module records time when the memory completely store the data packet according to the first notification signal and the second notification signal.

    Abstract translation: 提供了检测用于断电存储卡的超级电容器的功率服务时间的检测装置以及在检测到的服务时间期间能够存储的数据分组的量。 电源断开的存储卡包括一个存储器。 检测装置包括电源单元,超级电容器,控制器,存储单元和检测单元。 存储单元存储数据分组。 检测单元包括充电通知模块,数据通知模块和时间模块。 收费通知模块向时间模块生成第一通知信号。 当存储单元将数据包发送到存储器时,数据通知模块生成第二通知信号给时间模块。 时间模块记录存储器根据第一通知信号和第二通知信号完全存储数据包的时间。

    POLYLACTIC ACID BLOCK COPOLYMERS AND PREPARATION METHODS THEREOF
    36.
    发明申请
    POLYLACTIC ACID BLOCK COPOLYMERS AND PREPARATION METHODS THEREOF 有权
    聚氨酯嵌段共聚物及其制备方法

    公开(公告)号:US20130324680A1

    公开(公告)日:2013-12-05

    申请号:US13990541

    申请日:2011-11-29

    CPC classification number: C08G63/08 C08G63/60

    Abstract: Disclosed are a polylactic acid block copolymer and a preparation method thereof. The polylactic acid block copolymer comprises block A and block B, and is presented as B-b-A-b-B triblock structure, wherein the block A is a cyclic aromatic polyester oligomer block, and the block B is a polylactic acid block. The polylactic acid block copolymer is obtained by ring-opening copolymerization of a cyclic aromatic polyester oligomer and a lactide. Disclosed are another polylactic acid block copolymer and a preparation method thereof. The polylactic acid block copolymer comprises block A and block B, and is presented as B-b-A-b-B triblock structure, wherein the block A is an aromatic polyester block with two hydroxyl end groups, and the block B is a polylactic acid block. The polylactic acid block copolymer is obtained by ring-opening copolymerization of an aromatic polyester with two hydroxyl end groups and a lactide.

    Abstract translation: 公开了一种聚乳酸嵌段共聚物及其制备方法。 聚乳酸嵌段共聚物包括嵌段A和嵌段B,并且以B-b-A-b-B三嵌段结构的形式存在,其中嵌段A是环状芳族聚酯低聚物嵌段,嵌段B是聚乳酸嵌段。 聚乳酸嵌段共聚物通过环状芳族聚酯低聚物和丙交酯的开环共聚得到。 公开了另一种聚乳酸嵌段共聚物及其制备方法。 聚乳酸嵌段共聚物包含嵌段A和嵌段B,并且以B-b-A-b-B三嵌段结构的形式存在,其中嵌段A是具有两个羟基端基的芳族聚酯嵌段,嵌段B是聚乳酸嵌段。 聚乳酸嵌段共聚物通过芳族聚酯与两个羟基端基和丙交酯的开环共聚获得。

    Snubber circuit for buck converter
    37.
    发明授权
    Snubber circuit for buck converter 失效
    降压转换器的缓冲电路

    公开(公告)号:US08513931B2

    公开(公告)日:2013-08-20

    申请号:US13031621

    申请日:2011-02-22

    CPC classification number: H02M3/155 H02M2001/344

    Abstract: A snubber circuit for decreasing a voltage spike of a buck converter includes a resistor unit, a capacitor unit, a detecting unit, and a control unit. The resistor unit provides multiple groups of resistance values. The capacitor unit provides multiple groups of capacitance values. The detecting unit detects voltage spikes of the buck converter corresponding to each group of resistance values and capacitance values. The control unit selects each group of resistance and capacitance to respectively connect to the buck converter and determines a group of resistance and capacitance corresponding to a lowest voltage spike by comparing the detected voltage spikes with each other.

    Abstract translation: 用于降低降压转换器的电压尖峰的缓冲电路包括电阻单元,电容器单元,检测单元和控制单元。 电阻单元提供多组电阻值。 电容器单元提供多组电容值。 检测单元检测对应于每组电阻值和电容值的降压转换器的电压尖峰。 控制单元选择每组电阻和电容分别连接到降压转换器,并通过将检测到的电压尖峰相互比较来确定与最低电压尖峰相对应的一组电阻和电容。

    Output voltage adjustment circuit for buck circuits
    38.
    发明授权
    Output voltage adjustment circuit for buck circuits 失效
    降压电路的输出电压调整电路

    公开(公告)号:US08339119B2

    公开(公告)日:2012-12-25

    申请号:US13073980

    申请日:2011-03-28

    CPC classification number: H02M3/157 H02M2001/0025

    Abstract: An output voltage adjustment circuit for buck circuits includes a microcontroller, first to eighth keys, and a display unit. The first to eighth keys input voltage adjustment signals to the microcontroller. A first input pin of the microcontroller is connected to a voltage output terminal. A second resistor is connected between the first input pin of the microcontroller and ground. A first to a sixth input/output pin of the microcontroller are connected to the display unit. A first to an eighth output pin of the microcontroller are connected to a pulse width modulation (PWM) controller. The first to eighth keys are selectively activated to provide voltage adjustment signals to the microcontroller, sampling output voltages of the voltage output terminal, comparing with a predetermined voltage, controlling the PWM controller to fine tune the duty cycle to output a stable voltage from the voltage output terminal. The display unit displays the voltages on the voltage output terminal.

    Abstract translation: 用于降压电路的输出电压调节电路包括微控制器,第一至第八键和显示单元。 第一至第八键输入电压调节信号给微控制器。 微控制器的第一个输入引脚连接到电压输出端子。 第二个电阻连接在微控制器的第一个输入引脚和地之间。 微控制器的第一至第六输入/输出引脚连接到显示单元。 微控制器的第一至第八输出引脚连接到脉宽调制(PWM)控制器。 选择性地激活第一至第八键以向微控制器提供电压调整信号,与预定电压相比较,对电压输出端子的输出电压进行采样,控制PWM控制器以微调占空比以从电压输出稳定的电压 输出端子。 显示单元显示电压输出端子上的电压。

    Driver circuit
    39.
    发明授权
    Driver circuit 失效
    驱动电路

    公开(公告)号:US08314640B2

    公开(公告)日:2012-11-20

    申请号:US13110917

    申请日:2011-05-19

    CPC classification number: G06F1/26

    Abstract: A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted.

    Abstract translation: 驱动电路驱动脉宽调制(PWM)控制器。 驱动器电路包括使能电路,电源输入控制电路,稳定电路和放电电路。 稳压电路与PWM控制器电连接。 电源输入控制电路电连接在使能电路和稳定电路之间。 放电电路电连接在稳压电路和地之间。 响应于驱动电路正常工作,使能电路使得电源输入控制电路向稳定电路输出工作电压,并且响应于驱动电路重新启动的过程,使能电路使电源 输入停止向稳定电路输出电源。 在驱动器电路重新启动的过程中,放电电路将稳定电路的剩余电压引向地。

    Initialization of reference signal scrambling
    40.
    发明授权
    Initialization of reference signal scrambling 有权
    参考信号加扰初始化

    公开(公告)号:US08300587B2

    公开(公告)日:2012-10-30

    申请号:US12715353

    申请日:2010-03-01

    CPC classification number: H04J11/0069 H04L27/2613

    Abstract: A scrambling sequence is initialized using at least a cell identifier and an offset, and a physical downlink control information DCI is sent to a user equipment which indicates the offset. In more particular embodiments a user equipment-specific reference signal UE-RS is scrambled using the initialized scrambling sequence, and the scrambled UE-RS is sent to the UE for demodulating a downlink shared channel (PDSCH). In another exemplary embodiment the generated UE-RS is sent in a pilot part of a subframe transmission associated with the PDSCH and is for demodulating at least a data part of that subframe transmission. In a specific embodiment from the UE side, the UE receives the UE-RS and the DCI which indicates the offset, descrambles the UE-RS using a scrambling sequence that is initialized using a cell identifier and the indicated offset; and demodulates the PDSCH using the de-scrambled UE-RS.

    Abstract translation: 使用至少小区标识符和偏移来初始化加扰序列,并且向指示偏移的用户设备发送物理下行链路控制信息DCI。 在更具体的实施例中,使用初始化的加扰序列对用户设备专用参考信号UE-RS进行加扰,并且将加扰的UE-RS发送给用于解调下行链路共享信道(PDSCH)的UE。 在另一个示例性实施例中,所生成的UE-RS在与PDSCH相关联的子帧传输的导频部分中被发送,并且用于解调该子帧传输的至少一个数据部分。 在来自UE侧的特定实施例中,UE接收指示偏移的UE-RS和DCI,使用使用小区标识符和指示的偏移量初始化的加扰序列来解扰UE-RS; 并使用去加扰的UE-RS解调PDSCH。

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