Abstract:
A solar cell includes a semiconductor substrate, a doping layer, a quantum well layer, a first passivation layer, a second passivation layer, a first electrode and a second electrode. The semiconductor substrate has a front surface and a back surface, and the front surface of the semiconductor substrate includes nano-rods. The doping layer covers the surface of the nano-rods. The electrode layers cover the doping layer. The quantum well layer having at least one first doping region and at least one second doping region is disposed on the semiconductor substrate. The quantum well layer includes polycrystalline silicon germanium (Si1-xGex). The first passivation layer and the second passivation layer cover the first and the second doping regions of the quantum well layer, respectively. The first electrode and the second electrode are electrically connected to the first doping region and the second doping region of the quantum well layer, respectively.
Abstract:
An electronic module to be mounted on a mounting surface may include: a circuit board provided with a heat source, wherein a thermal via is formed through the circuit board and is in thermal contact with the heat source; and a potting material packaging the circuit board at least at the other side opposite to one side of heat source, wherein the potting material has a recess formed in at least part of an area corresponding to the thermal via at the other side of the circuit board and a thermal conductive material, which is thermal-conductively connected to the mounting surface, is filled in the recess.
Abstract:
An electrical parameter detection device is configured for detecting electrical parameters of a peripheral component interconnect (PCI) connector including a plurality of power pins. The electrical parameter detection device includes a processor module, a first detection module, and a second detection module. The processor module continuously detects voltage values of electric potentials provided by each of the power pins of the PCI connector using the first detection module, and determines time sequences of the electric potentials according to the voltage values of the electric potentials. Furthermore, the processor module detects the amount of power provided by each of the power pins of the PCI connector using the second detection module.
Abstract:
An overcurrent protection device includes a power input terminal, a power output terminal, a first signal terminal, a second signal terminal, a testing circuit, and a switch element. The power input terminal and the first signal terminal are connected to a power supply. The power output terminal and the second signal terminal are connected to a computer motherboard. If the first and second terminals are disconnected from each other when the computer motherboard works, the power supply stops working. The testing circuit includes a fixed resistor and a control chip parallel connected between the power input and output terminal. The control chip stores a predetermined voltage threshold, and detects voltage between the two terminals of the fixed resistor, and compares the measured voltage with the predetermined voltage threshold. The switch element disconnects the first and second signal terminals when the measured voltage is greater than the predetermined voltage threshold.
Abstract:
A detection device to detect a power serving time of a super capacitor for a power-disconnected storage card and an amount of the data packets capable of being stored during the detected serving time is provided. The power-disconnected storage card includes a memory. The detection device includes a power supply unit, the super capacitor, a controller, a storage unit, and a detection unit. The storage unit stores the data packets. The detection unit includes a charge notification module, a data notification module and a time module. The charge notification module generates a first notification signal to the time module. The data notification module generates a second notification signal to the time module when the storage unit transmits the data packet to the memory. The time module records time when the memory completely store the data packet according to the first notification signal and the second notification signal.
Abstract:
Disclosed are a polylactic acid block copolymer and a preparation method thereof. The polylactic acid block copolymer comprises block A and block B, and is presented as B-b-A-b-B triblock structure, wherein the block A is a cyclic aromatic polyester oligomer block, and the block B is a polylactic acid block. The polylactic acid block copolymer is obtained by ring-opening copolymerization of a cyclic aromatic polyester oligomer and a lactide. Disclosed are another polylactic acid block copolymer and a preparation method thereof. The polylactic acid block copolymer comprises block A and block B, and is presented as B-b-A-b-B triblock structure, wherein the block A is an aromatic polyester block with two hydroxyl end groups, and the block B is a polylactic acid block. The polylactic acid block copolymer is obtained by ring-opening copolymerization of an aromatic polyester with two hydroxyl end groups and a lactide.
Abstract:
A snubber circuit for decreasing a voltage spike of a buck converter includes a resistor unit, a capacitor unit, a detecting unit, and a control unit. The resistor unit provides multiple groups of resistance values. The capacitor unit provides multiple groups of capacitance values. The detecting unit detects voltage spikes of the buck converter corresponding to each group of resistance values and capacitance values. The control unit selects each group of resistance and capacitance to respectively connect to the buck converter and determines a group of resistance and capacitance corresponding to a lowest voltage spike by comparing the detected voltage spikes with each other.
Abstract:
An output voltage adjustment circuit for buck circuits includes a microcontroller, first to eighth keys, and a display unit. The first to eighth keys input voltage adjustment signals to the microcontroller. A first input pin of the microcontroller is connected to a voltage output terminal. A second resistor is connected between the first input pin of the microcontroller and ground. A first to a sixth input/output pin of the microcontroller are connected to the display unit. A first to an eighth output pin of the microcontroller are connected to a pulse width modulation (PWM) controller. The first to eighth keys are selectively activated to provide voltage adjustment signals to the microcontroller, sampling output voltages of the voltage output terminal, comparing with a predetermined voltage, controlling the PWM controller to fine tune the duty cycle to output a stable voltage from the voltage output terminal. The display unit displays the voltages on the voltage output terminal.
Abstract:
A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted.
Abstract:
A scrambling sequence is initialized using at least a cell identifier and an offset, and a physical downlink control information DCI is sent to a user equipment which indicates the offset. In more particular embodiments a user equipment-specific reference signal UE-RS is scrambled using the initialized scrambling sequence, and the scrambled UE-RS is sent to the UE for demodulating a downlink shared channel (PDSCH). In another exemplary embodiment the generated UE-RS is sent in a pilot part of a subframe transmission associated with the PDSCH and is for demodulating at least a data part of that subframe transmission. In a specific embodiment from the UE side, the UE receives the UE-RS and the DCI which indicates the offset, descrambles the UE-RS using a scrambling sequence that is initialized using a cell identifier and the indicated offset; and demodulates the PDSCH using the de-scrambled UE-RS.