SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR
    31.
    发明公开
    SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR 审中-公开
    ETEEM VEKTOR的SYSTEME UND VERFAHREN ZUR DATENEXTRAKTION

    公开(公告)号:EP3026549A2

    公开(公告)日:2016-06-01

    申请号:EP15190667.4

    申请日:2012-08-24

    Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

    Abstract translation: 公开了向量处理器中的数据提取的系统和方法。 在特定实施例中,向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素,用重新排序的数据元素填充置换网络的目的地寄存器,以及将重新排序的数据元素从目的地寄存器复制到存储器。

    SELECTIVE COUPLING OF AN ADDRESS LINE TO AN ELEMENT BANK OF A VECTOR REGISTER FILE
    37.
    发明公开
    SELECTIVE COUPLING OF AN ADDRESS LINE TO AN ELEMENT BANK OF A VECTOR REGISTER FILE 有权
    SELEKTIVE KOPPLUNG EINER ADRESSZEILE EINE ELEMENTBANK EINER VEKTORREGISTERDATEI-REGISTERDATEI

    公开(公告)号:EP2909713A1

    公开(公告)日:2015-08-26

    申请号:EP13780470.4

    申请日:2013-10-09

    Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

    Abstract translation: 一种方法包括根据选择模式,将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的第一元素库内存储的数据。

    PER THREAD CACHELINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS
    39.
    发明公开
    PER THREAD CACHELINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS 审中-公开
    GEMEINSAMEN PARTITIONIERTEN CACHESPEICHERN BEI MULTITHREAD-PROZESSOREN中的机械式FÜRPRO-THREAD-CACHEZEENZUWEISUNG

    公开(公告)号:EP2847684A1

    公开(公告)日:2015-03-18

    申请号:EP13723374.8

    申请日:2013-05-08

    CPC classification number: G06F12/0842 G06F12/0848 G06F12/0864

    Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

    Abstract translation: 用于在多线程处理器的共享分区高速缓存中分配高速缓存行的系统和方法。 存储器管理单元被配置为确定与要在高速缓存中分配的处理线程相关联的高速缓存条目的地址相关联的属性。 配置寄存器被配置为基于所确定的属性来存储高速缓存分配信息。 分配寄存器被配置为存储用于将高速缓存分割成两个或更多个部分的分区信息。 缓存条目基于配置寄存器和分区寄存器分配到高速缓存的一部分中。

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