公开(公告)号：EP4439634A2

公开(公告)日：2024-10-02

申请号：EP24194383.6

申请日：2016-07-28

Applicant: QUALCOMM Incorporated

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L21/56

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L21/4846 ,  H01L23/5389 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/040120130101 ,  H01L2224/0410520130101 ,  H01L2224/13120130101 ,  H01L2224/1622720130101 ,  H01L2224/1623720130101 ,  H01L2224/7320420130101 ,  H01L2224/8181520130101 ,  H01L2924/1433520130101 ,  H01L2924/1531120130101 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/1210520130101 ,  H01L2924/143420130101 ,  H01L2924/143220130101 ,  H01L2224/9620130101

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

公开(公告)号：EP3304593A1

公开(公告)日：2018-04-11

申请号：EP16728787.9

申请日：2016-05-24

Applicant: Qualcomm Incorporated

Inventor： LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/14 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

公开(公告)号：EP3132469A1

公开(公告)日：2017-02-22

申请号：EP15718725.3

申请日：2015-04-10

Applicant: Qualcomm Incorporated

Inventor： WE, Hong Bok ,  KIM, Chin-Kwan ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）衬底，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在电介质层和第二图案化金属层上形成非导电层。

公开(公告)号：EP3114707A1

公开(公告)日：2017-01-11

申请号：EP15710373.0

申请日：2015-03-04

Applicant: Qualcomm Incorporated

Inventor： KIM, Dong Wook ,  WE, Hong Bok ,  LEE, Jae Sik ,  GU, Shiqun

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) coupled to a first surface of the base portion, and an underfill (222) between the first die and the base portion. The base portion includes a dielectric layer (202), and a set of redistribution metal layers (230-260). In some implementations, the integrated device further includes an encapsulation material (220) that encapsulates the first die. In some implementations, the integrated device further includes a second die (208) coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects (280) on the base portion, the set of interconnects coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars (216) and the second die includes a second set of interconnect pillars (218).

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一裸片以及在第一裸片与基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电连接第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：EP3105787A1

公开(公告)日：2016-12-21

申请号：EP15706345.4

申请日：2015-02-11

Applicant: Qualcomm Incorporated

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L23/498 ,  H01L25/10

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

公开(公告)号：EP2965357A1

公开(公告)日：2016-01-13

申请号：EP14712934.0

申请日：2014-03-05

Applicant: Qualcomm Incorporated

Inventor： LISK, Durodami Joscelyn ,  RAMACHANDRAN, Vidhya ,  LEE, Jae Sik

IPC: H01L25/10

CPC classification number: H01L23/5384 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/1403

Abstract: A via-enabled package-on-package circuit includes a first package including a first package die having a plurality of through substrate vias (TSVs). The TSVs are configured to carry the input/output signaling for at least one second package die.