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公开(公告)号：AU4016985A
公开(公告)日：1985-09-26
申请号：AU4016985
申请日：1985-03-20
Applicant: SONY CORP
Inventor： KITAZATO NAOHISA , HAMADA OSAMU
IPC: G01D3/00 , G01D3/028 , G01H7/00 , G11B20/10 , H03G5/00 , H03G5/16 , H03H17/00 , H03H17/02 , H04R3/04
Abstract: A digital graphic equalizer includes a pulse-sequence generator for generating a sequence of pulse signals, a first digital signal processor for filtering the pulse signals to produce a filtered signal, a digital-to-analog converter responsive to the filtered signal for producing a calibrating signal, and a loudspeaker responsive to the calibrating signal for propagating a calibrating sound in a listening environment, the frequency characteristics of the calibrating sound being subject to modification by the listening environment. A detector detects the calibrating sound as propagated in the listening environment and produces a detection signal representative thereof. An analog-to-digital converter is responsive to the detection signal for producing a digital signal corresponding thereto, and a second digital signal processor is responsive to the digital signal for producing a plurality of frequency-divided signals. A spectrum analyzer is responsive to the frequency-divided signals for analyzing the frequency characteristics of the calibrating sound as propagated in the listening environment and producing a compensating signal adapted to compensate for the modification by the listening environment of the frequency characteristics of the calibrating sound.
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公开(公告)号：GB2115588A
公开(公告)日：1983-09-07
申请号：GB8302850
申请日：1983-02-02
Applicant: SONY CORP
Inventor： HAMADA OSAMU
IPC: G06F7/00 , G06F9/00 , G06F9/06 , G06F9/22 , G06F9/24 , G06F9/38 , G06F17/14 , G06F17/15 , H03H17/02 , G06F13/00
Abstract: Described is a digital signal processor including at least two memories, that is, a microprogram memory for storing a series of microinstructions for instructing a digital signal processing procedure, and a coefficient memory for storing coefficient data required for performing a series of arithmetic operations on the digital signal data. These data being transferred and written into said microprogram memory and said coefficient memory from a host computer system. The coefficient memory has at least two pages corresponding to the total memory area which may be addressed during digital signal processing to be effected by said microinstructions. Page selection of the coefficient memory may be performed from said host computer system.
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公开(公告)号：DE3303488A1
公开(公告)日：1983-09-01
申请号：DE3303488
申请日：1983-02-02
Applicant: SONY CORP
Inventor： HAMADA OSAMU
IPC: G06F7/00 , G06F9/00 , G06F9/06 , G06F9/22 , G06F9/24 , G06F9/38 , G06F17/14 , G06F17/15 , H03H17/02 , G06F13/06 , G06F3/06 , G11B5/09
Abstract: Described is a digital signal processor including at least two memories, that is, a microprogram memory for storing a series of microinstructions for instructing a digital signal processing procedure, and a coefficient memory for storing coefficient data required for performing a series of arithmetic operations on the digital signal data. These data being transferred and written into said microprogram memory and said coefficient memory from a host computer system. The coefficient memory has at least two pages corresponding to the total memory area which may be addressed during digital signal processing to be effected by said microinstructions. Page selection of the coefficient memory may be performed from said host computer system.
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公开(公告)号：DE3013250A1
公开(公告)日：1980-10-23
申请号：DE3013250
申请日：1980-04-03
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: A digital waveform generating apparatus includes a key assignor selecting a frequency of a signal to be generated, a number-setting circuit for generating a first data word corresponding to the selected frequency, a first memory for storing said first data word, a second memory for storing a second data word, an accumulator for accumulating the first data word onto the second data word stored in the second memory, so that the second data word stored in the second memory after accumulating represents the sum of the second data word immediately prior thereto added with said first data word, a waveform memory, preferably an ROM, for storing predetermined waveform data and for generating a waveform data output signal, and a control circuit for controlling such accumulating and progressively addressing the waveform memory in accordance with the stored second data word at the time of a timing signal. Preferably, the number-setting circuit generates a plurality of the first data words corresponding to at least one corresponding frequency, the first and second memories have a plurality of channels storing the first data word and the second data words to be added with the first data words, and the control circuit operates in a time-sharing fashion. To avoid folded errors in the output signal, the waveform memory can include a plurality of data banks each storing waveform data corresponding to a predetermined portion of the frequency range of the apparatus, and the control circuit operates to select an appropriate data bank corresponding to the selected frequency.
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公开(公告)号：AU5709580A
公开(公告)日：1980-10-09
申请号：AU5709580
申请日：1980-04-02
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: A digital waveform generating apparatus includes a key assignor selecting a frequency of a signal to be generated, a number-setting circuit for generating a first data word corresponding to the selected frequency, a first memory for storing said first data word, a second memory for storing a second data word, an accumulator for accumulating the first data word onto the second data word stored in the second memory, so that the second data word stored in the second memory after accumulating represents the sum of the second data word immediately prior thereto added with said first data word, a waveform memory, preferably an ROM, for storing predetermined waveform data and for generating a waveform data output signal, and a control circuit for controlling such accumulating and progressively addressing the waveform memory in accordance with the stored second data word at the time of a timing signal. Preferably, the number-setting circuit generates a plurality of the first data words corresponding to at least one corresponding frequency, the first and second memories have a plurality of channels storing the first data word and the second data words to be added with the first data words, and the control circuit operates in a time-sharing fashion. To avoid folded errors in the output signal, the waveform memory can include a plurality of data banks each storing waveform data corresponding to a predetermined portion of the frequency range of the apparatus, and the control circuit operates to select an appropriate data bank corresponding to the selected frequency.
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Patent Agency Ranking
公开(公告)号：CA1055125A
公开(公告)日：1979-05-22
申请号：CA223326
申请日：1975-03-27
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: A pulse width modulated signal amplifier including a signal input circuit, a clock pulse generating circuit, a pulse phase modulating circuit and a pair of pulse transformers. The pulse phase modulating circuit is supplied with the output signal of the signal input circuit and the clock pulse signal in such a manner as to produce a pair of pulse signals having a phase difference which is proportional to the output signal level of the signal input circuit. Each primary coil of the transformer is supplied with a pair of pulse signals, and the secondary coils are connected so as to add and subtract the pulse signals respectively. A rectifying circuit is supplied with the output signals from the secondary coils so as to produce the finally constituted pulse width modulated signals where the width of the pulse is proportional to the output signal level of the signal input circuit. At the same instance it is applied to a load through a low pass filter.
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公开(公告)号：CA1052447A
公开(公告)日：1979-04-10
申请号：CA312726
申请日：1978-10-05
Applicant: SONY CORP
Inventor： HAMADA OSAMU
IPC: H04B1/26
Abstract: A broadcast receiver having a tuner with a variable local oscillator for generating a local frequency signal, a divider for dividing the local frequency signal at a variable dividing ratio, a comparator for comparing the divided local frequency output with a reference signal by which the local oscillator frequency is controlled, a counter having a variable content by which the dividing ratio of the divider is determined for establishing the radio broadcast frequency to which the receiver is tuned, a pulse generator operative to vary the counter content, and a detector circuit for producing an audio signal in response to an output from the tuner. The broadcast receiver further provides with non-voltaic memory device for memorizing contents of the counter at the time when the counter contents change, means for reading out the signal stored in the non-voltaic memory means and presetting the read out signal in the counter when a power source for the receiver is made ON, and a muting circuit for muting the audio signal during the operation of counter for selection.
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公开(公告)号：CA1043431A
公开(公告)日：1978-11-28
申请号：CA294942
申请日：1978-01-13
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: A protective circuit for a pulse width modulated signal amplifier includes a signal input circuit, a carrier signal generator, a pulse width modulator for receiving both the output signals of the signal input circuit and the carrier signal generator and for producing a pulse width modulated signal, an amplifier for receiving the pulse width modulated signal and for amplifying it to drive a load through a low pass filter, a detecting circuit for detecting whether the pulse width modulated signal is present or not, or detecting DC voltage of undesirable duration produced at the output of the amplifier and for producing a control signal, and a protective circuit for receiving the control signal so as to cut off the operation of the amplifier when it is present. - i
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公开(公告)号：CA1034215A
公开(公告)日：1978-07-04
申请号：CA228497
申请日：1975-06-04
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: A pulse width modulated signal amplifier system includes a signal input circuit, an amplifier for receiving an input signal from the signal input circuit, a pulse width modulator for receiving an output signal from the amplifier and producing a pulse width modulated signal, and a phase splitter for receiving the pulse width modulated signal and producing a pair of corresponding pulse width modulated signals having different polarities to each other. The system further includes a first demodulator for receiving one of the pair of pulse width modulated signals and demodulating a first output signal having one polarity and an amplitude in response to the input signal, a second demodulator for receiving the other of the pair of pulse width modulated signals and producing a second output signal having the other polarity and an amplitude in response to the input signal, a load supplied with the first and second output signals, an amplitude comparator for comparing the first and second output signals and producing a control signal in response to the comparison result, and a feedback circuit for receiving the control signal and applying it to the amplifier so as to balance the first and second output signal amplitudes.
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