公开(公告)号：US20230371269A1

公开(公告)日：2023-11-16

申请号：US18195522

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Kiheun Lee ,  Daewon Ha

IPC: H10B51/30 ,  H10B51/10 ,  H01L29/78 ,  H01L21/28

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/78391 ,  H10B51/10

Abstract: A memory device includes a channel region, a conductive electrode on the channel region, and a data storage structure between the channel region and the conductive electrode. The data storage structure includes a stack structure including two-dimensional material layers and ferroelectric layers stacked alternately and repeatedly in a direction perpendicular to a surface of the channel region. A thickness of each of the ferroelectric layers is greater than a thickness of each of the two-dimensional material layers.

公开(公告)号：US20230309314A1

公开(公告)日：2023-09-28

申请号：US18108374

申请日：2023-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok Kim ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/10 ,  H01L29/51 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/516 ,  H01L29/78391

Abstract: A three-dimensional ferroelectric random access memory (3D FeRAM) device includes: a gate electrode extending in a vertical direction on a substrate; a ferroelectric pattern and a gate insulation pattern stacked on the gate electrode in a horizontal direction to surround the gate electrode; first and second channels spaced apart from each other in the horizontal direction on an outer sidewall of the gate insulation pattern; first source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the first channel; and second source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the second channel.

公开(公告)号：US20230178440A1

公开(公告)日：2023-06-08

申请号：US17677329

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： MING HE ,  Jaehyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L27/0922 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0665

Abstract: Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.

公开(公告)号：US20230178420A1

公开(公告)日：2023-06-08

申请号：US17679465

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  JaeHyun Park ,  Chihak Ahn ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76283 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/6653

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

公开(公告)号：US20230046546A1

公开(公告)日：2023-02-16

申请号：US17699724

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

公开(公告)号：US20220231134A1

公开(公告)日：2022-07-21

申请号：US17325083

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo ,  Daewon Ha ,  Jason Martineau

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

公开(公告)号：US11004981B2

公开(公告)日：2021-05-11

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soonmoon Jung ,  Daewon Ha ,  Sungmin Kim ,  Hyojin Kim ,  Keun Hwi Cho

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US10804403B2

公开(公告)日：2020-10-13

申请号：US16437056

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon Ha ,  Seungseok Ha ,  Byoung Hak Hong

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US20250098224A1

公开(公告)日：2025-03-20

申请号：US18967518

申请日：2024-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US20250072041A1

公开(公告)日：2025-02-27

申请号：US18945638

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Daewon Ha

IPC: H01L29/78 ,  H01L29/417

Abstract: An integrated circuit device according to the inventive concept includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a stopper layer that is above and spaced apart from the fin-type active area; a gate electrode extending in a second horizontal direction orthogonal to the first horizontal direction, on the fin-type active area, and in a space between the fin-type active area and the stopper layer; and a gate capping layer on upper surfaces of the gate electrode and the stopper layer.