公开(公告)号：US20190164807A1

公开(公告)日：2019-05-30

申请号：US15823149

申请日：2017-11-27

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Anindya Poddar ,  Usman Mahmood Chaudhry

IPC: H01L21/768 ,  H01L23/498 ,  H05K1/18 ,  B81B7/00 ,  H01L23/04 ,  H01L23/31 ,  H01L21/822 ,  H01L23/00

Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

公开(公告)号：US20150008566A1

公开(公告)日：2015-01-08

申请号：US14320803

申请日：2014-07-01

Applicant: Texas Instruments Incorporated

Inventor： Mark A. Gerber ,  Mutsumi Masumoto ,  Kenji Masumoto ,  Anindya Poddar ,  Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).

Abstract translation: 一种以面板格式制造封装半导体器件的方法; 将具有开口的面板尺寸的金属网格放置在胶带（292）上; 将具有用于芯片端子的具有窗口的聚合物层的半导体芯片附接到带（293）上; 层压低CTE绝缘材料以填充芯片和网格之间的间隙（294）; 翻转组件以将载体放置在芯片的背面和层压之下并去除带（295）; 等离子体清洁组件正面，横跨组装的溅射均匀金属层（296）; 可选地镀金属层（297）; 并且图案化溅射层以形成重新布线迹线和用于组装的扩展接触垫（298）。

公开(公告)号：US20250087591A1

公开(公告)日：2025-03-13

申请号：US18960733

申请日：2024-11-26

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US20240421120A1

公开(公告)日：2024-12-19

申请号：US18816640

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming a stress sensitive component on a first semiconductor die; forming a solder seal on the first semiconductor die, the solder seal extending from a first surface of the first semiconductor die, and surrounding the stress sensitive component, the solder seal having an interior surface that surrounds the stress sensitive component and having an exterior surface facing away from the stress sensitive component; flip chip mounting the first semiconductor die to a first surface of a second semiconductor die, the stress sensitive component facing the first surface of the second semiconductor die; and forming a solder joint between the solder seal and the first surface of the second semiconductor die.

公开(公告)号：US12125799B2

公开(公告)日：2024-10-22

申请号：US17517608

申请日：2021-11-02

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3735 ,  H01L23/49861

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US20240347441A1

公开(公告)日：2024-10-17

申请号：US18753858

申请日：2024-06-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Edgar Dorotyao Balidoy ,  Hau Nguyen ,  Makoto Yoshino ,  MING LI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/49844 ,  H01L24/48 ,  H05K1/0204 ,  H01L2224/48177 ,  H01L2224/48178 ,  H01L2224/48248 ,  H01L2224/48465 ,  H01L2924/1811 ,  H01L2924/182

Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

公开(公告)号：US12074134B2

公开(公告)日：2024-08-27

申请号：US17364769

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L24/95 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

公开(公告)号：US11942384B2

公开(公告)日：2024-03-26

申请号：US17515234

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Hideaki Matsunaga ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/4952 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/48245

Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

公开(公告)号：US20230275007A1

公开(公告)日：2023-08-31

申请号：US17683074

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Masamitsu Matsuura ,  Kengo Aoya ,  Anindya Poddar

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49555 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/85 ,  H01L21/565 ,  H01L21/4842 ,  H01L2224/48245 ,  H01L24/32 ,  H01L2224/32245 ,  H01L24/73 ,  H01L2224/73265

Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

公开(公告)号：US20220108955A1

公开(公告)日：2022-04-07

申请号：US17517608

申请日：2021-11-02

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/373

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.