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    SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
    32.
    发明申请
    SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF 有权
    感应芯片包装及其制造方法

    公开(公告)号：US20170040372A1

    公开(公告)日：2017-02-09

    申请号：US15226327

    申请日：2016-08-02

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

    Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。

    CHIP PACKAGE AND METHOD OF FABRICATING THE SAME
    33.
    发明申请
    CHIP PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20150255499A1

    公开(公告)日：2015-09-10

    申请号：US14621240

    申请日：2015-02-12

    Applicant: XINTEC INC.

    Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Chien-Hung LIU

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14621 ,  H01L27/14685 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity.

    Abstract translation: 芯片封装包括半导体芯片，绝缘层，再分配层和封装层，并且形成有空腔。 半导体芯片具有电子部件和导电焊盘。 导电焊盘和电子部件设置在半导体芯片的上表面上并电连接。 该空腔从半导体芯片的下表面开口并朝向上表面逐渐变细以暴露导电垫。 绝缘层涂覆下表面和空腔的一部分。 绝缘层形成有间隙以暴露导电垫。 再分布层包覆下表面和空腔的一部分，并通过间隙电连接到导电垫。 包装层涂覆下表面和空腔的一部分。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    36.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20130316499A1

    公开(公告)日：2013-11-28

    申请号：US13958398

    申请日：2013-08-02

    Applicant: XINTEC INC.

    Inventor： Ching-Yu NI ,  Chia-Ming CHENG ,  Nan-Chun LIN

    IPC: H01L21/78

    CPC classification number: H01L23/498 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

    Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。 多个导电焊盘设置在外围接合焊盘区域处，并且钝化层形成在半导体衬底上以露出导电焊盘。 在器件区域的钝化层上形成绝缘保护层。 封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。 该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘，并且通过封装层的开口去除导电焊盘上的绝缘保护层。

    POWER MOSFET PACKAGE
    37.
    发明申请
    POWER MOSFET PACKAGE 有权
    功率MOSFET封装

    公开(公告)号：US20130193520A1

    公开(公告)日：2013-08-01

    申请号：US13828537

    申请日：2013-03-14

    Applicant: Xintec Inc.

    Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG ,  Ching-Yu NI ,  Yun-Jui HSIEH ,  Wei-Ming CHEN ,  Chia-Lun TSAI ,  Chia-Ming CHENG

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

    Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

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