公开(公告)号：JPH0667876A

公开(公告)日：1994-03-11

申请号：JP21620392

申请日：1992-08-13

Applicant: YAMAHA CORP

Inventor： MORISHIMA MORIHITO

IPC: G06F9/28 ,  G06F9/38 ,  G06F15/78

Abstract: PURPOSE:To execute rapid signal processing by connecting respective arithmetic means to respective storage means in accordance with a microcode generated by a microcode generating means and allowing respective arithmetic means to execute the arithmetic processing of data supplied from respective storage means in parallel. CONSTITUTION:A microcode RAM-U stores microcodes corresponding to various signal processing. Information is written in a selecting register US through output switching circuits OX1 to OXn. Respective memory parts MEM1 to MEMn are used for the delay processing of digital signals, the temporary storage of intermediate results in various signal processing, the temporary storage of control information relating to signal processing, and so on. For instance, the memory part MEM1 consists of a dual port RAM 11, a modulo counter 12 and adders 13, 14. A parallel operation part PCAL has plural I/O ports and plural arithmetic means and respective arithmetic means execute respective arithmetic processing in parallel at the time of receiving supplied input data.

公开(公告)号：JPH04196815A

公开(公告)日：1992-07-16

申请号：JP32759290

申请日：1990-11-28

Applicant: YAMAHA CORP

Inventor： MORISHIMA MORIHITO

IPC: H01L21/82 ,  G06F17/50 ,  H03K19/177

Abstract: PURPOSE:To simplify an algorithm of a wiring pulling around or the like by operating the feedback of the output of a clock delay circuit to an input side as necessary in order to operate the layout of a logical circuit. CONSTITUTION:When a prescribed processing is executed after defining signals inputted to clock delay circuits 1 and 7 respectively as signals D01' and D02', and signals outputted from the clock delay circuits 1 and 7 respectively as signals D01 and D02, a logical expression indicating each output signal ST and STP of the logical circuit is searched. Then, the necessary clock delay circuits are connected with the output stages of each product terms sum constituting a PLA(Programmable Logic Array), and the output of the clock delay circuit is operated for the feedback to the input side as necessary, in order to operate the layout of the logical circuit. Thus, the algorithm of the wiring pulling around or the like is simplified.

公开(公告)号：JPH04188910A

公开(公告)日：1992-07-07

申请号：JP31746890

申请日：1990-11-21

Applicant: YAMAHA CORP

Inventor： MORISHIMA MORIHITO

IPC: H03K3/354

Abstract: PURPOSE:To unnecessitate the adjustment of an oscillation frequency or the like without being affected by a process fluctuation or a temperature change by supplying driving currents which change according to a control voltage to each gate of the first and forth field effect transistors (FET), and operating an oscillating operation according to the control voltage. CONSTITUTION:This circuit is equipped with a current generating means Tr 3 which supplies the driving currents which change according to the control voltage supplied from the outside to each gate of first and forth RET 2a and 2d. Then, the oscillation frequency changes according to a current Ir. That is, this current Ir is controlled according to the control voltage supplied to a control voltage input terminal Tin, so that a voltage control oscillating circuit(VCO) can be realized. Thus, this circuit is difficult to be affected by the process fluctuation or the temperature change at the time of forming an LSI, and the fluctuation of the oscillation frequency can be reduced.

公开(公告)号：JPH02110739A

公开(公告)日：1990-04-23

申请号：JP26447688

申请日：1988-10-20

Applicant: YAMAHA CORP

Inventor： MORISHIMA MORIHITO

IPC: G06F9/46 ,  G06F9/48

Abstract: PURPOSE:To decrease the loss of a time due to an interrupting processing when the multi-task processing is carried out by switching so that a task set corresponding to the task in which a CPU is presently executed can be selected by a task register and can be operated based on an arithmetic unit. CONSTITUTION:A task set 7a is composed of a program counter 1a, an accumulator 2a, a register 3a and a flag register 4a, the same number of the task sets 7a as the program is prepared and at the time of executing one program, one set is used. Each time three programs A to C are switched for a certain constant time and for a T time, task sets 7a to 7c corresponding to respective programs A to C are selected by a task register 5, switching is executed so as to operate based on the arithmetic unit and the action is repeated until respective programs are completed. Thus, at the time of being the multi-task processing, the time loss at the time of changing the program can be decreased.

公开(公告)号：JP2011077739A

公开(公告)日：2011-04-14

申请号：JP2009225754

申请日：2009-09-30

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO

IPC: H03F3/217 ,  H03F3/181

Abstract: PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of suitable amplification with reduced power consumption or the like. SOLUTION: The amplifier circuit (100) includes an amplification part (50) and a power supply circuit part (20) for supplying a power supply voltage to the amplification part. The power supply circuit part of them includes a plurality of transistors (Tr1-Tr6) shown in the figure, a modulation part (10) for controlling their on/off, and first and second capacitive elements (C1, C2), etc., in addition to a coil (L) provided between a first node (ND1) and a second node (ND2). The modulation part generates pulse width modulation signals (OUTPG and OUTNG, etc.) corresponding to input signals, controls the on/off of the respective transistors using the signals, controls the direction of a current flowing to the coil, and selects the capacitive element (C1 or C2) to be charged. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供能够以降低的功耗等进行适当放大的放大器电路。 解决方案：放大器电路（100）包括放大部分（50）和用于向放大部分提供电源电压的电源电路部分（20）。 其电源电路部分包括图中所示的多个晶体管（Tr1-Tr6），用于控制它们的导通/截止的调制部分（10）和第一和第二电容元件（C1，C2）等， 除了设置在第一节点（ND1）和第二节点（ND2）之间的线圈（L）之外。 调制部生成与输入信号对应的脉冲宽度调制信号（OUTPG，OUTNG等），利用该信号控制各晶体管的导通/截止，控制流向线圈的电流的方向，并选择电容元件 （C1或C2）充电。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009175560A

公开(公告)日：2009-08-06

申请号：JP2008015734

申请日：2008-01-28

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO

IPC: G10H7/08

CPC classification number: G10H7/004 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3853 ,  G06F9/3885

Abstract: PROBLEM TO BE SOLVED: To provide a sound generator apparatus processing at high speed and reconfiguring functions dynamically. SOLUTION: The sound generator apparatus 100 includes: an operation section A for executing a plurality of types of instructions by performing arithmetic operations using a plurality of hardware-implemented arithmetic operation elements; and a control section B for reading out a program from a program memory 84 to execute the read-out program. The plurality of types of instructions include: a first extended instruction for instructing that an arithmetic operation for generating envelope data to control variation over time of a sound volume should be performed using data read out from a working memory 83 and the arithmetic operation elements; a second extended instruction for instructing that an arithmetic operation for generating phase data to control a frequency of a waveform should be performed using data read out from a working memory 83 and the arithmetic operation elements; and a third extended instruction for instructing that an arithmetic operation for generating result data should be performed using the envelope and phase data and the arithmetic operation elements. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种高速处理的声音发生器装置和动态重新配置功能。 解决方案：声音发生装置100包括：操作部分A，用于通过使用多个硬件实现的算术运算元件执行算术运算来执行多种类型的指令; 以及用于从程序存储器84读出程序以执行读出程序的控制部分B. 多种类型的指令包括：用于指示用于产生包络数据以控制音量随时间变化的算术运算的第一扩展指令应使用从工作存储器83和算术运算元件读出的数据来执行; 用于指示用于产生相位数据以控制波形频率的算术运算的第二扩展指令应该使用从工作存储器83和算术运算元件读出的数据来执行; 以及用于指示使用包络和相位数据和算术运算元件来执行用于生成结果数据的算术运算的第三扩展指令。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009152819A

公开(公告)日：2009-07-09

申请号：JP2007328273

申请日：2007-12-20

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO

IPC: H03F3/217 ,  H03K3/017

CPC classification number: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To suppress electromagnetic interference caused by pulse-width modulation.
SOLUTION: A time period control unit 30 controls a time length TU of each unit term U in a variable manner. A pulse-width modulating unit 20 is arranged by a holding unit 22, a counting unit 24, and a waveform generating unit 26. The holding unit 22 holds a plurality of data XD which are sequentially supplied for every unit term U as data XE. The counting unit 24 changes a count value C during each unit term U. The waveform generating unit 26 generates such a pulse-width modulating signal S that pulses P are arranged for every unit term U, while time points when a large/small relationship between the count value C and a numeral value of the data XE held by the holding unit 22 is inverted are defined as edge portions of the pulses.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：抑制由脉冲宽度调制引起的电磁干扰。 解决方案：时间段控制单元30以可变的方式控制每个单位项U的时间长度TU。 脉冲宽度调制单元20由保持单元22，计数单元24和波形发生单元26布置。保持单元22保持为每个单位项U顺序提供的多个数据XD作为数据XE。 计数单元24在每个单位项U期间改变计数值C.波形发生单元26产生这样的脉冲宽度调制信号S，脉冲P布置在每个单位项U上，而时间点当时间点之间大的/小的关系 计数值C和由保持单元22保持的数据XE的数值被反转定义为脉冲的边缘部分。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007299525A

公开(公告)日：2007-11-15

申请号：JP2007185999

申请日：2007-07-17

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO ,  USUI AKIRA ,  SHIOZAKI YOSHIHIKO

IPC: G11B7/0045 ,  G11B7/24 ,  G11B23/40

Abstract: PROBLEM TO BE SOLVED: To record visible information in a thermosensitive plane of an optical disk in addition to information recording for a recording plane without providing individually a new apparatus or the like. SOLUTION: When recording data is supplied from a host PC 110, the recording data is supplied to a laser driver 19 through a buffer memory 36, an encoder 17, and a strategy circuit 18, an optical disk D is irradiated with a laser beam in accordance with the recording data, and information is recorded. On the other hand, when picture data is supplied from the host PC 110, the picture data is supplied to the laser driver 19 through the buffer memory 36, a control part 16, a FIFO memory 34, and a drive pulse generating part 35, a laser beam corresponding to the picture data is irradiated, and a visible picture is formed on the thermosensitive plane of the optical disk D. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：除了单独提供新的装置等之外，还可以将除了记录面的信息记录之外的可见信息记录在光盘的热敏平面中。 解决方案：当从主机PC1提供记录数据时，记录数据通过缓冲存储器36，编码器17和策略电路18提供给激光驱动器19，光盘D被照射 激光束根据记录数据，并记录信息。 另一方面，当从主机110提供图像数据时，图像数据通过缓冲存储器36，控制部分16，FIFO存储器34和驱动脉冲产生部分35提供给激光驱动器19， 照射对应于图像数据的激光束，并且在光盘D的热敏平面上形成可视图像。（C）2008，JPO＆INPIT

公开(公告)号：JP2007242232A

公开(公告)日：2007-09-20

申请号：JP2007126925

申请日：2007-05-11

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO

IPC: G11B7/0045 ,  G11B23/40

Abstract: PROBLEM TO BE SOLVED: To prevent cost increase and to form an image on an optical disk at high speed and in high quality.
SOLUTION: The optical disk device is provided in which recording data of 24 bytes supplied from a host computer is subjected to framing, pits specified by a bit string signal of data subjected to framing are formed successively, and dot data specifying density of the dot of an image to be formed in the optical disk is replaced with recording data and supplied from a host computer when the image is formed. To the optical disk device, a discriminating device 1565 discriminating whether a part corresponding to dot data out of bit string signals is predetermined value or not is added, and a gate circuit 1567 which when the discriminated result is affirmative, passes the bit string signals therethrough over a dot period required for forming a picture of one dot, while when the discriminated result is negative, intercepts the bit string signals over the dot period is also added.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了防止成本增加并且以高速和高质量在光盘上形成图像。 解决方案：提供了一种光盘装置，其中从主计算机提供的24字节的记录数据进行成帧，连续形成经受成帧的数据的位串信号指定的凹坑，以及指定密度的 要在光盘中形成的图像的点被替换为记录数据，并且当形成图像时从主计算机提供。 鉴别装置1565与光盘装置相加，鉴别装置1565是否与比特串信号中的点数据相对应的部分是否为预定值;以及门电路1567，当鉴别结果为肯定时，将比特串信号通过 在形成一个点的图像所需的点周期之间，而当鉴别结果为负时，也加上在点周期上截取位串信号。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006060549A

公开(公告)日：2006-03-02

申请号：JP2004240701

申请日：2004-08-20

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MORISHIMA MORIHITO

IPC: H03F3/217 ,  H04R3/00

Abstract: PROBLEM TO BE SOLVED: To provide a digital amplifier which has a simple and inexpensive configuration and can drive a speaker with arbitrary high voltage and attain complete digitalization in a small LSI (large scale integrated circuit). SOLUTION: An arithmetic circuit 1 operates a difference between an input signal vi and a feedback signal Fb. A PWM (pulse width modulation) circuit 2 converts an output of the arithmetic circuit 1 into a pulse width modulated signal. A waveform conversion circuit 3 consists of a switch transistor that is subjected to on/off control by an output of the PWM circuit 2, a coil inserted with the switch transistor in series and a capacitor charged by induced current of the coil, and converts the output of the PWM circuit 2 into a high voltage analog signal to supply the high voltage analog signal to a load 4. In addition, an amplifier 5 amplifies the output of the PWM circuit 2 and returns the amplified output to the arithmetic circuit 1 as the feedback signal Fb. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种数字放大器，其具有简单且便宜的配置，并且可以驱动具有任意高电压的扬声器并且在小型LSI（大规模集成电路）中获得完整的数字化）。 解决方案：算术电路1操作输入信号vi和反馈信号Fb之间的差。 PWM（脉冲宽度调制）电路2将运算电路1的输出转换为脉宽调制信号。 波形转换电路3由通过PWM电路2的输出进行开关控制的开关晶体管，串联开关晶体管的线圈和由线圈的感应电流充电的电容器， PWM电路2的输出为高电压模拟信号，以将高电压模拟信号提供给负载4.此外，放大器5放大PWM电路2的输出，并将放大的输出返回到运算电路1，作为 反馈信号Fb。 版权所有（C）2006，JPO＆NCIPI