公开(公告)号：JP2009077003A

公开(公告)日：2009-04-09

申请号：JP2007241789

申请日：2007-09-19

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： SUZUKI MASAYA ,  TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03K5/08

CPC classification number: H03K5/2472

Abstract: PROBLEM TO BE SOLVED: To provide a comparator capable of comparing two voltages which are comparison objects as large voltage values as they are and outputting the signals of a low voltage value that the circuit of the post stage can receive and process as the signals indicating a comparison result.
SOLUTION: The comparator includes: P channel field effect transistors 11 and 12 which are supplied with input voltages V
in and V
ref being comparison objects at respective gates and which act as a differential transistor pair; and N channel field effect transistors 15 and 16 which function as the current paths of the respective drain currents of the two P channel field effect transistors and act as a current mirror circuit, and the comparator outputs the drain voltage V
x of the N channel field effect transistor 16 as a comparison result signal for the two input voltages, wherein a diode-connected N channel field effect transistor 14 is interposed between the drains of the N channel field effect transistors 16 and 15.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种比较器，其能够比较作为比较对象的两个电压作为大电压值，并输出后级的电路可以接收并处理的低电压值的信号作为 指示比较结果的信号。

解决方案：比较器包括：被提供有和V SB SB中的输入电压V SB的P沟道场效应晶体管11和12是各个门的比较对象， 作为差分晶体管对; 和N沟道场效应晶体管15和16，其用作两个P沟道场效应晶体管的相应漏极电流的电流路径，并且用作电流镜电路，并且比较器输出漏极电压V SB， SB>作为两个输入电压的比较结果信号，其中二极管连接的N沟道场效应晶体管14插在N沟道场效应晶体管16和15的漏极之间。

版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009044380A

公开(公告)日：2009-02-26

申请号：JP2007206310

申请日：2007-08-08

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KOIDE MASARU ,  TANAKA TAISHIN ,  KAWAI HIROKATA ,  SUZUKI MASAYA

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To attain reduction in distortion when a minute signal is inputted in a class-D amplifier circuit. SOLUTION: An up-down counter 70 outputs such a signal that a delay amount in a delay amount variable circuit 50 becomes large, and such a signal that the delay amount becomes small. Output of the both signals is usually performed alternatively or complementarily. More specifically, the delay amount is gradually increased by the former, and the delay amount is gradually reduced by the latter. Thus, widths of output pulses OutP, OutM gradually increase or gradually decrease. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：当在D类放大器电路中输入微小信号时，可以减小失真。 解决方案：升降计数器70输出延迟量可变电路50的延迟量变大的信号，延迟量变小的信号。 两个信号的输出通常是交替地或互补地执行。 更具体地，延迟量由前者逐渐增加，延迟量由后者逐渐减小。 因此，输出脉冲OutP，OutM的宽度逐渐增加或逐渐减小。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008060423A

公开(公告)日：2008-03-13

申请号：JP2006236896

申请日：2006-08-31

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN

IPC: H01L23/12 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide an IC chip which can be mounted on a plurality of types of package, and to provide a semiconductor device packaging that IC chip. SOLUTION: The IC chip comprises an amplifying circuit 20, a first pad electrode 21 connected with the output of the amplifying circuit 20, a feedback circuit provided with a feedback resistor 23 having resistance R1 and connecting the first pad electrode 21 with the input of the amplifying circuit 20, a resistor 27 provided between the first pad electrode 21 and the feedback resistor 23, and a second pad electrode 22 provided between the resistor 27 and the feedback resistor 23. When packaging with QFP structure, a lead terminal on the package side and the first pad electrode 21 are connected by a bonding wire. When packaging with CSP structure, output terminal of the package, i.e. a solder ball 103, is connected with the first pad electrode 21 by first rewiring 101 and the solder ball 103 is connected with the second pad electrode 22 by second rewiring 102. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可以安装在多种类型的封装上的IC芯片，并提供IC芯片的半导体器件封装。 解决方案：IC芯片包括放大电路20，与放大电路20的输出端连接的第一焊盘电极21，设置有具有电阻R1的反馈电阻器23并将第一焊盘电极21与 放大电路20的输入，设置在第一焊盘电极21和反馈电阻器23之间的电阻器27以及设置在电阻器27和反馈电阻器23之间的第二焊盘电极22.当用QFP结构封装时，引线端子 封装侧和第一焊盘电极21通过接合线连接。 当使用CSP结构封装时，通过第一重新布线101将封装的输出端子即焊球103与第一焊盘电极21连接，并且焊球103通过第二重新布线102与第二焊盘电极22连接。

版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008060422A

公开(公告)日：2008-03-13

申请号：JP2006236895

申请日：2006-08-31

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a compact semiconductor device which can feed back the output signal from a package.
SOLUTION: The semiconductor device comprises a feedback circuit consisting of an IC chip 2 in which an amplifying circuit 20 is formed and having a first pad electrode 21 connected with the output of the amplifying circuit 20, first rewiring 101 connected with the first pad electrode 21 and arranged on the circuit forming surface of the IC chip 2 through a polyimide film 106, a second pad electrode 22 connected with the first rewiring 101 and provided on the IC chip 2 while having a solder ball 103 for taking out the output from the amplifying circuit 20, second rewiring 102 connected with the solder ball 103 and the second pad electrode 22 and arranged on the circuit forming surface of the IC chip 2 through the polyimide film 106, and wiring for connecting the input of the amplifying circuit 20 with the second pad electrode 22, and inputting a feedback signal to the amplifying circuit 20.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够从封装反馈输出信号的小型半导体器件。 解决方案：半导体器件包括由IC芯片2组成的反馈电路，其中形成放大电路20，并且具有与放大电路20的输出连接的第一焊盘电极21，与第一重新布线连接的第一重新布线101 焊盘电极21，其通过聚酰亚胺膜106配置在IC芯片2的电路形成面上;第二焊盘电极22，与第一重新布线101连接并设置在IC芯片2上，同时具有用于取出输出的焊球103 从放大电路20，与焊球103连接的第二重新布线102和第二焊盘电极22通过聚酰亚胺膜106布置在IC芯片2的电路形成表面上，以及用于连接放大电路20的输入的布线 与第二焊盘电极22相连，并将反馈信号输入到放大电路20.版权所有：（C）2008，JPO＆INPIT

公开(公告)号：JP2008017369A

公开(公告)日：2008-01-24

申请号：JP2006188718

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03G3/20 ,  H03G3/30

Abstract: PROBLEM TO BE SOLVED: To provide an automatic gain control circuit capable of preventing a clip by decreasing gain of amplifying input audio signals when there is a possibility of occurrence of the clip in the power amplifier of a post-stage. SOLUTION: A control section 100 updates data LVLm denoting the level division of the input audio signals on the basis of a signal CMP denoting the result of comparison between the input audio signals and a reference level Vr and also controls the reference level Vr thereby controlling the gain of electronic volumes 10L, 10R to reach gain correlated with the level division of the input audio signals. In this case, the level division of the input audio signals and the gain are correlated with each other so that the level of an output signal of each of the electronic volumes does not exceed a preset output amplitude upper limit level. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种自动增益控制电路，其能够通过在后级功率放大器中存在夹子的可能性时减小放大输入音频信号的增益来防止剪辑。 解决方案：控制部分100基于表示输入音频信号与参考电平Vr之间的比较结果的信号CMP来更新表示输入音频信号的电平分割的数据LVLm，并且还控制参考电平Vr 从而控制电子体积10L，10R的增益以达到与输入音频信号的电平分割相关的增益。 在这种情况下，输入音频信号和增益的电平分割相互关联，使得每个电子卷的输出信号的电平不超过预设的输出幅度上限电平。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017354A

公开(公告)日：2008-01-24

申请号：JP2006188624

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03F3/34 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To provide an offset voltage correcting circuit capable of suppressing the fluctuations in the amount of offset voltage correction to a change in environment, and of accurately correcting the offset voltage of a differential amplifier.
SOLUTION: The offset voltage correcting circuit of the differential amplifier has NMOS transistors 100, 101 that are a pair of differential transistors; and PMOS transistors 102, 103 that are a pair of load transistors connected between the output section of the pair of differential transistors and a power supply VDD. Between one source of the pair of load transistors and the power supply, a voltage generation means is provided for generating a fixed voltage for correcting the offset voltage of the differential amplifier.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种能够抑制偏移电压校正量随着环境变化而变动的偏移电压校正电路，并且能够精确地校正差分放大器的偏移电压。 解决方案：差分放大器的偏移电压校正电路具有作为一对差分晶体管的NMOS晶体管100,101; 以及作为一对负载晶体管的PMOS晶体管102,103，其连接在一对差分晶体管的输出部和电源VDD之间。 在一对负载晶体管的一个源极和电源之间提供电压产生装置，用于产生用于校正差分放大器的偏移电压的固定电压。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017309A

公开(公告)日：2008-01-24

申请号：JP2006188196

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H04J13/00 ,  H03K3/353 ,  H03K5/156 ,  H04B1/69 ,  H04B1/7136

CPC classification number: H04B1/7136 ,  H04B2001/71365 ,  H04B2001/7154

Abstract: PROBLEM TO BE SOLVED: To surely reduce unwanted electromagnetic emission with a simple construction.
SOLUTION: A controller 20 generates in one sequence designation signals C11 to C52 designating total of a plurality of frequencies different from those previously designated by selection from a plurality of frequencies. A signal generator 10 having current supplying units U1 to U5, generates a triangular wave TRI by charging and discharging constant current from and to a capacitance element 12. A comparison circuit 13 compares the triangular wave TRI to an upper limit voltage ULMT and lower limit voltage DLMT. A clock signal generating circuit 14 generates a first clock signal CK1 and a second clock signal CK2 based on the compared results.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：确保以简单的结构减少不必要的电磁辐射。 解决方案：控制器20以一个序列产生指定信号C11至C52，指定与先前由多个频率进行选择指定的多个频率不同的多个频率的总和。 具有电流供应单元U1至U5的信号发生器10通过从恒定电容元件12充电和放电恒定电流而产生三角波TRI。比较电路13将三角波TRI与上限电压ULMT和下限电压 DLMT。 时钟信号发生电路14基于比较结果产生第一时钟信号CK1和第二时钟信号CK2。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017268A

公开(公告)日：2008-01-24

申请号：JP2006187708

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H03F1/52 ,  H03F3/217 ,  H03K17/08 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To prevent each switching element from being damaged greatly for protection when overcurrent occurs in the switching element of an output stage in a class D amplifier.
SOLUTION: When the overcurrent of, for example, a transistor NP in an output buffer circuit 10 exceeds a permissible value, a current limiting section 60NP limits the drain current of the transistor NP to a current limitation target value immediately, thus reducing damage to the transistor NP even if the operation of a current breaking section 30, where transistors PP, PM, NP, NM are turned off according to the detection of the overcurrent, is delayed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了防止在D类放大器的输出级的开关元件中发生过电流时，为了保护而防止每个开关元件被大大损坏。 解决方案：当例如输出缓冲电路10中的晶体管NP的过电流超过允许值时，限流部分60NP将晶体管NP的漏极电流立即限制为电流限制目标值，从而减小 即使根据过电流的检测关闭晶体管PP，PM，NP，NM的电流断路部30的动作，也延迟对晶体管NP的损坏。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004072276A

公开(公告)日：2004-03-04

申请号：JP2002226628

申请日：2002-08-02

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: H03K17/687 ,  H03F3/217 ,  H03F3/30

CPC classification number: H03F3/2171

Abstract: PROBLEM TO BE SOLVED: To provide a D-class amplifier which can control driving of an output power MOS transistor without using special circuit technology and electronic parts.
SOLUTION: A complementary signal generation circuit 301 generates first complementary signals (S1 and S2) from a PWM signal. A signal conversion circuit 302 converts the first complementary signals into second complementary signals (S3, S4 or S5 and S6) having a voltage component where a negative power source VPP- is set to be a reference. The signals S3 and S4 in the second complementary signals are supplied to a driving circuit 305, and the signals S5 and S6 are supplied to a current driving circuit 303. The current driving circuit 303 outputs third complementary signals (H3 and H4) having current components toward the negative power source VPP- in response to the signals S5 and S6 to a driving circuit 304. Thus, the driving circuits 304 and 305 complementarily drive power MOS transistors 401 and 402.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004064673A

公开(公告)日：2004-02-26

申请号：JP2002223606

申请日：2002-07-31

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: H04R3/00 ,  H03F1/52 ,  H03F3/185 ,  H03F3/187 ,  H03F3/217 ,  H03F3/393 ,  H03K17/08 ,  H03K17/695

CPC classification number: H03F3/2171 ,  H03F3/185 ,  H03F3/393

Abstract: PROBLEM TO BE SOLVED: To provide a class D amplifier wherein both power MOS transistors constituting the output stage can be controlled to an off state when an excess output current is generated.
SOLUTION: Detecting circuits (REFH, CM11, LA1, TN1, RN1) which detect an excess current flowing in the power MOS transistor 401 of the output stage and output a first signal (ITN1) are arranged in a first driving circuit 303H of a high side driver side. Detecting circuits (REFL, CM21, LA2, TN2, RN2) which detect an excess current flowing in the power MOS transistor 402 of the output stage and output a second signal (ITN2) are arranged in a driving circuit 303L of a low side driver side. The first signal (ITN1) is converted to a third signal (ITT2) wherein a negative power source VPP- is made a reference by using a signal conversion circuit. The third signal is added to the second signal. In response to the added signal, a pulse signal to be input in the driving circuits 303H, 303L is obstructed.
COPYRIGHT: (C)2004,JPO