公开(公告)号：US20060197225A1

公开(公告)日：2006-09-07

申请号：US11074106

申请日：2005-03-07

Applicant: Qi Pan ,  Jiutao Li ,  Yongjun Hu ,  Allen McTeer

Inventor： Qi Pan ,  Jiutao Li ,  Yongjun Hu ,  Allen McTeer

IPC: H01L23/52 ,  H01L21/44 ,  H01L29/772 ,  H01L21/8234

CPC classification number: H01L21/76838 ,  H01L21/28061 ,  H01L21/28518 ,  H01L21/2855 ,  H01L23/485 ,  H01L27/10891 ,  H01L29/4933 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括导电线，形成导电线的方法，以及在多晶硅晶体管栅极线上制造钛硅化物时还原钛硅化物聚集的方法。 在一个实施方案中，形成导电线的方法包括在衬底上提供含硅层。 在含硅层之上形成导电层。 在导电层上方形成了一个MSi x N N y S y - 含量，其中“x”为0至3.0，“y”为0.5至10，以及 “M”是Ta，Hf，Mo和W中的至少一种。在MSi x N y y上，形成MSiZb含量层。 其中“z”为1〜3.0。 在MSiZ包含层上形成TiSi 1 a含量层，其中“a”为1至3.0。 包含硅的层，导电层，包含MSi x N的混合层，包含MSi的混合层和 将TiSi 1 a含有层图案化成包括导电线的堆叠。 考虑了其他方面和实现。

公开(公告)号：US20060062710A1

公开(公告)日：2006-03-23

申请号：US11100573

申请日：2005-04-07

Applicant: Yongjun Hu ,  Er-Xuan Ping

Inventor： Yongjun Hu ,  Er-Xuan Ping

IPC: B01J27/24

CPC classification number: B01J37/0244 ,  B01J21/08 ,  B01J23/40 ,  B01J23/74 ,  B01J27/24 ,  B01J37/0238

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

公开(公告)号：US06998341B2

公开(公告)日：2006-02-14

申请号：US10771828

申请日：2004-02-04

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/4763

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal silicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种用于制造光滑并具有大的扩散阻挡材料的氮化物晶粒的膜的方法。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境氮含量，使得扩散阻挡材料的氮化物核均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长扩散阻挡材料的大的氮化物晶粒的膜。 还公开了一种适合于MOS存储器电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻度氮化难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US20060017107A1

公开(公告)日：2006-01-26

申请号：US11012049

申请日：2004-12-14

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L27/12

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

公开(公告)号：US20050181599A1

公开(公告)日：2005-08-18

申请号：US11071922

申请日：2005-03-04

Applicant: Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

Inventor： Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/45 ,  C04B35/00 ,  H01L21/20 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

Abstract translation: 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US20050123464A1

公开(公告)日：2005-06-09

申请号：US10793880

申请日：2004-03-08

Applicant: Yongjun Hu ,  Er-Xuan Ping

Inventor： Yongjun Hu ,  Er-Xuan Ping

IPC: B01J21/08 ,  B01J27/24 ,  B01J37/02

CPC classification number: B01J37/0244 ,  B01J21/08 ,  B01J23/40 ,  B01J23/74 ,  B01J27/24 ,  B01J37/0238

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

Abstract translation: 一种通过在衬底上形成半球形晶粒多晶硅的第一层并且氧化至少一部分第一层以形成第二层二氧化硅来形成催化剂体的方法。 此外，在退火之前可以在第二层上形成第三层氮化物材料，并在氮化物层上形成催化剂材料以形成催化剂体。

公开(公告)号：US20050110058A1

公开(公告)日：2005-05-26

申请号：US10719047

申请日：2003-11-20

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L29/76

CPC classification number: H01L27/105 ,  H01L23/485 ,  H01L27/1052 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a conductive nitride layer on the conductive barrier layer. Next, a conductive amorphous layer is formed on the conductive barrier layer, and an elemental metal layer is formed on the conductive amorphous layer. Without the conductive amorphous layer the elemental metal layer would form on the conductive nitride layer as a small grained, high resistance layer, while it forms on the conductive amorphous layer as a large grained, low resistance layer. A semiconductor device which may be formed using this method is also described.

公开(公告)号：US06753584B1

公开(公告)日：2004-06-22

申请号：US09476558

申请日：2000-01-03

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L310232

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/318 ,  H01L21/32139 ,  H01L27/1462 ,  H01L31/02161 ,  H01L31/02327 ,  Y10S430/151

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns. One preferred material for the inventive antireflective layer includes metal silicon nitride ternary compounds of the general formula MxSiyNz wherein M is at least one transition metal, x is less than y, and z is in a range from about 0 to about 5y. Preferably, the Si will exceed M by about a factor of two. Addition of N is controlled by the ratio in the sputtering gas such as Ar/N. Tungsten is a preferred transition metal in the fabrication of the inventive antireflective coating. A preferred tungsten silicide target will have a composition of silicon between 1 and 4 in stoichiometric ratio to tungsten. Composite antireflective layers made of metal silicide binary compounds or metal silicon nitride ternary compounds may be fashioned according to the present invention depending upon a specific application.

Abstract translation: 根据本发明的抗反射结构包括层叠的金属氮化硅组合物，该层被叠加在待图案化的层上，这将在光致抗蚀剂图案化期间另外引起破坏性的反射率。 抗反射结构具有吸收光致抗蚀剂图案化期间使用的光的能力。 抗反射结构还具有将未吸收的光散射到对暴露于图案和强度的光致抗蚀剂材料无效的图案和强度的能力。本发明的优选的抗反射结构包括其上具有至少一层含硅的 金属或含硅金属氮化物。 半导体衬底将优选地具有宽度尺寸小于约0.5微米，更优选小于约0.25微米的特征尺寸。用于本发明的抗反射层的一种优选材料包括通式为MxSiyNz的金属氮化硅三元化合物，其中M为 至少一种过渡金属x小于y，z在约0至约5y的范围内。 优选地，Si将超过M约2倍。 N的添加由溅射气体中的比例如Ar / N控制。 在本发明的抗反射涂层的制造中，钨是优选的过渡金属。 优选的硅化钨靶将具有与钨的化学计量比为1至4的硅组成。 由金属硅化物二元化合物或金属氮化硅三元化合物制成的复合抗反射层可根据具体应用根据本发明制成。

公开(公告)号：US06214711B1

公开(公告)日：2001-04-10

申请号：US09139583

申请日：1998-08-25

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L213205

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.

Abstract translation: 通过将合金或复合靶溅射到凹槽中，将合金或复合材料沉积在半导体衬底的凹陷特征中，以形成第一沉积材料层。 第一沉积材料层以低角度和低能量被重新投射，以将第一沉积材料层重新沉积到凹槽的底部上，作为具有不同于第一沉积材料的化学计量的第二沉积材料层。 在另一实施例中，溅射室环境由氩和氮组成。 在又一个实施例中，再溅射步骤之后是沉积具有与第二沉积层不同的化学计量比的至少一层材料，以形成沉积在凹槽中的材料的“分级”化学计量。

公开(公告)号：US5863393A

公开(公告)日：1999-01-26

申请号：US964575

申请日：1997-11-05

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: C23C14/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01L21/768

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.

Abstract translation: 通过将合金或复合靶溅射到凹槽中，将合金或复合材料沉积在半导体衬底的凹陷特征中，以形成第一沉积材料层。 第一沉积材料层以低角度和低能量被重新投射，以将第一沉积材料层重新沉积到凹槽的底部上，作为具有不同于第一沉积材料的化学计量的第二沉积材料层。 在另一实施例中，溅射室环境由氩和氮组成。 在又一个实施例中，再溅射步骤之后是沉积具有与第二沉积层不同的化学计量比的至少一层材料，以形成沉积在凹槽中的材料的“分级”化学计量。