公开(公告)号：JP2012195550A

公开(公告)日：2012-10-11

申请号：JP2011113621

申请日：2011-05-20

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： LIN JEN-WEI

IPC: H01L21/02

CPC classification number: H01L21/67288

Abstract: PROBLEM TO BE SOLVED: To provide an abnormality prediction control device and method for a semiconductor manufacturing facility capable of following the life and predicting the damage of the semiconductor manufacturing facility, reducing a down time of the facility and a time required for restoration, and preventing a large amount of abnormalities in products.SOLUTION: An abnormality prediction control device 200 for a semiconductor manufacturing facility 100 has a multichannel transmitter 210 connected between a first vibration detector 220 and a vibration spectrum analysis device 240. The multichannel transmitter 210 includes a multichannel connection module 212 having a plurality of signal connection terminals 213. The signal connection terminal 213 is connected with the first vibration detector 220, and with a first control signal connection wire 230 through which to connect with a first controller 120 corresponding to a first rotation type frequency conversion device 110. Thereby, life following and early damage prediction of the semiconductor manufacturing facility can be performed, and a down time of the facility and a time required for restoration can be reduced.

Abstract translation: 要解决的问题：提供一种用于半导体制造设备的异常预测控制装置和方法，其能够跟随寿命并预测半导体制造设备的损坏，减少设备的停机时间和恢复所需的时间 ，防止产品的异常量大。 解决方案：用于半导体制造设备100的异常预测控制装置200具有连接在第一振动检测器220和振动频谱分析装置240之间的多通道发射器210.多通道发射器210包括多通道连接模块212，多通道连接模块212具有多个 信号连接端子213与第一振动检测器220连接，并且与第一控制信号连接线230连接，第一控制信号连接线230与第一控制器120连接，对应于第一旋转型变频器110。 ，可以进行半导体制造设备的生命跟踪和早期损伤预测，并且可以减少设备的停机时间和恢复所需的时间。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2010073994A

公开(公告)日：2010-04-02

申请号：JP2008241434

申请日：2008-09-19

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： CHEN CHIN-TI

IPC: H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/83 ,  H01L24/32 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

Abstract: PROBLEM TO BE SOLVED: To provide a window type BGA package which suppresses peeling or rapture of the side surface. SOLUTION: The window type BGA package includes: a substrate 210; a first chip 220; a die attach member 230; a plurality of first bonding wires 240; a sealing body 250; and a plurality of circumscribing terminals 260. The substrate 210 includes a die attach recess 213 and a slot 214. The first chip 220 is set on the die attach recess 213 and includes a side surface 223. The die attach member 230 is formed in the die attach recess 213. The die attach recess 213 restricts the shape of the die attach member 230, and the die attach member 230 is filled in the gap between the side surfaces 223 and a peripheral edge 213A, covering a part of the side surfaces 223. The first bonding wires 240 pass by the slot 214 so that the first chip 220 and the substrate 210 are electrically connected together. The sealing body 250 seals the first chip 220 and the first bonding wires 240. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供抑制侧面剥离或破裂的窗型BGA封装。 解决方案：窗型BGA封装包括：衬底210; 第一芯片220; 管芯附接构件230; 多个第一接合线240; 密封体250; 和多个外接端子260.基板210包括管芯安装凹部213和槽214.第一芯片220设置在管芯附接凹部213上并且包括侧表面223.管芯附接构件230形成在 管芯安装凹部213限制管芯安装构件230的形状，并且将管芯安装构件230填充在侧面223之间的间隙和覆盖一部分侧面223的周缘213A 第一接合线240通过狭槽214，使得第一芯片220和基板210电连接在一起。 密封体250密封第一芯片220和第一接合线240.版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010021185A

公开(公告)日：2010-01-28

申请号：JP2008177856

申请日：2008-07-08

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L23/12 ,  H01L21/52

CPC classification number: H01L24/32 ,  H01L24/73 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package substrate capable of preventing remaining bubbling of a die-attaching agent and overflow thereof. SOLUTION: A group of first fingers 321, a group of second fingers 322 and a group of third fingers 323 are provided on a surface 311 of a substrate body 310. The group of first fingers 321 are positioned between the groups of second and third fingers 322 and 323. A solder mask layer 330 is formed on the surface 311 and has a first opening 331, a second opening 332 and a third opening 333 exposing the groups of first, second and third fingers 321, 322 and 323, respectively. A first gas discharge groove portion 340 is formed on the exposed surface of the solder mask layer 330, does not extend through the solder mask layer 330, is connected to the first opening 331 and extends to sides 313, 314 of the surface 311, and does not couple together with the second opening 332 and the third opening 333. In this manner, since the semiconductor package has a passage for discharging a gas to the outside, retention of the bubbles of the die-attaching agent are prevented. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供能够防止管芯附着剂残留的起泡和溢流的半导体封装基板。 解决方案：一组第一指状物321，一组第二指状物322和一组第三指状物323设置在基底主体310的表面311上。第一指状物组321位于第二手指组 和第三指322和323。在表面311上形成焊接掩模层330，并且具有暴露第一，第二和第三指状物321,322和323的组的第一开口331，第二开口332和第三开口333， 分别。 第一气体排出槽部分340形成在焊料掩模层330的暴露表面上，不延伸穿过焊料掩模层330，连接到第一开口331并延伸到表面311的侧面313,314，以及 不与第二开口332和第三开口333耦合。以这种方式，由于半导体封装具有用于将气体排放到外部的通道，因此防止了管芯附着剂的气泡的保留。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009283663A

公开(公告)日：2009-12-03

申请号：JP2008134067

申请日：2008-05-22

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： WANG CHIN-FA ,  HSIEH WAN JUNG ,  HSU YU-MEI

IPC: H01L23/50

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package which increases the chip-mounting strength and avoids inclination and displacement of chips, fracture of a bonding wire, and exposure of leads.
SOLUTION: The semiconductor package includes: a first lead 210; a second lead 220 having a first finger 211, a second finger 221; a tie rod 230 placed between the first lead 210 and the second lead 220; a chip 240, having a plurality of bonding pads 241 adhered on the first lead 210, second lead 220 and the tie rod 230; a plurality of bonding wires 251, 252 which connects the bonding pads 241 group respectively to the first finger 211, the second finger 221, a sealing body 260 which seals a part of the first lead 210 and a second lead 220, the tie rod 230, the chip 240; and the bonding wires 251, 252 group, wherein the tie rod 230 has an extended portion that forms a junction with a side border of the sealing body 260, and forms a circular arc bent portion.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高芯片安装强度并避免芯片倾斜和位移，接合线断裂以及引线暴露的半导体封装。 解决方案：半导体封装包括：第一引线210; 具有第一手指211，第二手指221的第二引线220; 放置在第一引线210和第二引线220之间的拉杆230; 芯片240具有粘附在第一引线210上的多个接合焊盘241，第二引线220和拉杆230; 连接接合焊盘241的多个接合线251,252分别组合到第一手指211，第二指状物221，密封第一引线210的一部分的密封体260和第二引线220，拉杆230 ，芯片240; 并且接合线251,252组成，其中拉杆230具有与密封体260的侧边界形成结的延伸部分，并形成圆弧弯曲部分。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009260201A

公开(公告)日：2009-11-05

申请号：JP2008150145

申请日：2008-06-09

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： CHEN CHIN-TI ,  WANG CHIN-FA

IPC: H01L23/50 ,  H01L23/12

CPC classification number: H01L23/49565 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a chip mounting device for improving the identification of semi-finished packaged chips during a chip package process and further decreasing the possibility of erroneous identification by operators. SOLUTION: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. On the side rail, at least one identifying element is included. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在芯片封装处理期间改进半成品封装芯片的识别的芯片安装装置，并进一步降低操作者错误识别的可能性。 解决方案：芯片安装装置包括至少一个芯片安装单元和在芯片安装单元旁边配置的至少一个侧导轨。 芯片安装单元包括芯片焊盘和多个导电触点。 在侧轨上包括至少一个识别元件。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009212461A

公开(公告)日：2009-09-17

申请号：JP2008056615

申请日：2008-03-06

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： CHEN CHIN-TI ,  WANG CHIN-FA ,  YU BING-SHUN

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/49171 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01082 ,  Y02P80/30 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an identification code which can shorten time required to identify a failure wire bonding machine. SOLUTION: A chip 110 having a plurality of bonding pads 111 is installed in a loading body 120 having a plurality of fingers 121. One binary system code reference line 130 is set on the loading body 120 to divide a finger 121 group into a first code area 122 and a second code area 123 by the binary system code reference linea 130. A bonding wire 140 group electrically connecting the bonding pad 111 group and the finger 121 group by a wire bonding method is jointed to any of the first code area 122 or the second code area 123 of the finger 121 group to configure the identification code of the wire bonding machine. According to such the method, the failure wire bonding machine can swiftly be traced by the identification code. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成识别码的方法，其可以缩短识别故障引线接合机所需的时间。 解决方案：具有多个接合焊盘111的芯片110安装在具有多个指状物121的装载体120中。一个二进制系统代码参考线130设置在装载主体120上以将手指121组分成 通过二进制系统代码参考线130的第一代码区域122和第二代码区域123.通过引线接合方法将接合焊盘111组和手指121组电连接的接合线140组合到任何第一代码 区域122或手指121组的第二代码区域123构成引线接合机的识别码。 根据这种方法，故障引线接合机可以通过识别码快速追踪。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009124071A

公开(公告)日：2009-06-04

申请号：JP2007299132

申请日：2007-11-19

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L25/10 ,  H01L23/50 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L2225/1029 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a stacked assembly of semiconductor packages, in which the adhesion at high temperatures and the solder joint area of leads are increased to enhance the impact durability.
SOLUTION: A stacked assembly of semiconductor packages comprises a first semiconductor package 210 and at least one second semiconductor package 220. The first semiconductor package 210 comprises at least a first chip 211, multiple first outer leads 212 of a leadframe, and a first encapsulant 213. The second semiconductor package 220, which is mounted onto the first semiconductor package 210, comprises at least a second chip 221, two or more second outer leads 222 of a leadframe, and a second encapsulant 223. The second outer leads 222 are exposed on the outside of the second encapsulant 223. At least each second outer lead 222 has a U-shaped recessed cut end surface which is solder-joined to the joint of the corresponding first outer lead 212.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供半导体封装的堆叠组装，其中提高高温下的粘合性和引线的焊点面积以增强冲击耐久性。 解决方案：半导体封装的堆叠组件包括第一半导体封装210和至少一个第二半导体封装220.第一半导体封装210包括至少第一芯片211，引线框的多个第一外引线212和 第一密封剂213.安装在第一半导体封装210上的第二半导体封装220包括至少第二芯片221，引线框的两个或更多个第二外引线222和第二密封剂223.第二外引线222 暴露在第二密封剂223的外部。至少每个第二外引线222具有U形凹入的切割端表面，其焊接到相应的第一外引线212的接头。版权所有（C） ）2009，JPO＆INPIT

公开(公告)号：JP2009099749A

公开(公告)日：2009-05-07

申请号：JP2007269630

申请日：2007-10-17

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package such that a crevice in a solder bonding interface can be prevented from spreading. SOLUTION: The semiconductor package has a chip carrier 210, a chip 220, and a plurality of tower-like bumps 230. The chip carrier 210 has an upper surface 211 and a lower surface 212 where the plurality of first guide bonding pads 213 are installed. The chip 220 is installed or electrically connected to the chip carrier 210. The tower-like bumps 230 are made to correspond to or are installed at a first guide bonding pad group 213 for the use as external solder bonding. Each tower-like bump 230 has at least a first crevice suppressing ring, which suppresses spreading of a solder crevice almost in parallel to the first guide bonding pad 213. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体封装，使得可以防止焊接界面中的缝隙扩散。 解决方案：半导体封装具有芯片载体210，芯片220和多个塔状凸起230.芯片载体210具有上表面211和下表面212，其中多个第一引导键合焊盘 213安装。 芯片220安装或电连接到芯片载体210.塔状凸起230被制成对应于或者被安装在第一引导键合焊盘组213上，用作外部焊接接合。 每个塔状凸块230至少具有第一缝隙抑制环，其抑制焊接缝隙的扩散几乎与第一引导键合焊盘213平行。版权所有：（C）2009，JPO＆INPIT

公开(公告)号：JP2009054741A

公开(公告)日：2009-03-12

申请号：JP2007219196

申请日：2007-08-27

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L25/10 ,  H01L25/11 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package avoiding a solder joining defect due to warpage of a substrate.
SOLUTION: The semiconductor package 200 has a first semiconductor package 210, a package carrier 220 and a solder material 230. The solder material 230 is used to solder and join external terminals 213 and 214 of the semiconductor package 210 to the package carrier 220. The external terminals 213 and 214 of the semiconductor package 210 are divided into at least two groups because of difference in distances from the center line of the substrate. The external connection terminals 213 and 214 in the different groups have bumps differing in height for compensation of solder material gap differences occurring when the groups of the external connection terminals 213 and 214 and the package carrier 220 are joined owing to the predicted warpage of the substrate and then the warpage of the substrate is predicted to suppress the occurrence of the solder joining defect.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供避免由于基板翘曲引起的焊料接合缺陷的半导体封装。 解决方案：半导体封装200具有第一半导体封装210，封装载体220和焊料230.焊料230用于将半导体封装210的外部端子213和214焊接到封装载体 由于与基板的中心线的距离不同，半导体封装210的外部端子213和214被分成至少两个组。 不同组中的外部连接端子213和214具有高度不均的凸起，用于补偿由于基板的预测翘曲而导致的外部连接端子213和214以及封装载体220的组合时发生的焊料间隙差异 然后预测基板的翘曲来抑制焊料接合缺陷的发生。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008177347A

公开(公告)日：2008-07-31

申请号：JP2007009204

申请日：2007-01-18

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG ,  FANG LI-CHIH

IPC: H01L23/12

CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an IC chip package structure having a die attach layer near the substrate size.
SOLUTION: The IC chip package structure includes a substrate 210 having an upper surface 211 and a lower surface 212 for forming a plurality of ball pads 213, a die attach layer 220 which is nearly equal to the substrate in size and is formed substantially on the upper surface 211 to cover a part corresponding to a ball pad 213 group excepting the periphery, a chip 230 which is mounted on the upper surface 211, has an active face for forming a plurality of bonding pads, and is bonded to the first part 221 of the die attach layer 220 nearly equal to the substrate in size, a bonding wire for connecting a bonding pad group electrically with the substrate 210, a sealing body 250 formed on the upper surface 211 to cover the second part 222 of the die attach layer 220 nearly equal to the substrate in size and completely sealing the die attach layer 220 nearly equal to the substrate in size and a bonding wire group hermetically, and a solder ball 260 arranged on the ball pad 213 group.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供在基板尺寸附近具有管芯附着层的IC芯片封装结构。 解决方案：IC芯片封装结构包括具有上表面211和用于形成多个焊盘213的下表面212的基板210，与基板尺寸几乎相等的芯片附着层220 基本上在上表面211上覆盖与外围的球垫213组对应的部分，安装在上表面211上的芯片230具有用于形成多个接合焊盘的有源面，并且被接合到 芯片附着层220的大致等于基板的第一部分221，用于将焊盘组与基板210电连接的接合线，形成在上表面211上以覆盖第二部分222的密封体250 芯片附着层220的尺寸几乎等于基板，并且将密封基片的芯片附着层220大致完全密封，并且密封焊丝组，以及布置在球垫213组上的焊球260。 版权所有（C）2008，JPO＆INPIT