RADAR APPARATUS AND LEAKAGE CORRECTION METHOD

    公开(公告)号:EP3647808A1

    公开(公告)日:2020-05-06

    申请号:EP19205609.1

    申请日:2019-10-28

    Abstract: A radar apparatus (1, 1', 1") and a leakage correction method thereof are provided. The radar apparatus (1, 1', 1") includes a transmitter (100, 100') and a receiver (200, 200', 200'-1, 200", 200"-1). The receiver (200, 200', 200'-1, 200", 200"-1) receives transmitting signals (TS) including a sinewave signal (SS1) from the transmitter (100, 100'). The sinewave signal generator (210, 210') of the receiver (200, 200', 200'-1, 200", 200"-1) generates another sinewave signal (SS2) according to the amplitude of the transmitting signals (TS) or received transmitting signals (RTS). The correcting circuit (250) corrects leakage situation (LS) on the received transmitting signals (RTS) according to another sinewave signal (SS2). The phasor of sinewave form corresponding to the leakage situation (LS) relates to the phasor of another sinewave signal (SS2). Accordingly, the performance of receiver (200, 200', 200'-1, 200", 200"-1) may be improved effectively.

    VOLTAGE GENERATOR WHICH CAN SUPPORT ASSOCIATED CIRCUITRY
    32.
    发明公开
    VOLTAGE GENERATOR WHICH CAN SUPPORT ASSOCIATED CIRCUITRY 审中-公开
    SPANNUNGSGENERATOR,DER EINE VERBUNDENE SCHALTUNGSBAUGRUPPEUNTERSTÜTZENKANN

    公开(公告)号:EP3032730A1

    公开(公告)日:2016-06-15

    申请号:EP15198594.2

    申请日:2015-12-09

    CPC classification number: H02M3/24 H02M1/36 H02M3/07 H02M7/103 H02M2003/075

    Abstract: A voltage generator (100) includes an oscillator (130), a charge pump (140) having an input and an output, the input of the charge pump (140) being coupled to the output of the oscillator (130), a first resistor (R1) connected to the output of the charge pump (140), a second resistor (R2) connected to the first resistor (R1), a smoothing capacitor (C1) connected to the second resistor (R2), and a shorting element (150) connected in parallel with the second resistor (R2). When the shorting element is turned on, the second resistor (R2) is bypassed. By including an adjustable regulated voltage regulator (160), an adjustable bias current generator (160) and a size-adjustable inverter module (170), the voltage generator (100) is able to manipulate the speed of voltage generation.

    Abstract translation: 电压发生器(100)包括振荡器(130),具有输入和输出的电荷泵(140),电荷泵(140)的输入耦合到振荡器(130)的输出端,第一电阻器 (R1)连接到电荷泵(140)的输出端,连接到第一电阻器(R1)的第二电阻器(R2),连接到第二电阻器(R2)的平滑电容器(C1)和短路元件 150)与第二电阻器(R2)并联连接。 当短路元件接通时,旁路第二电阻器(R2)。 通过包括可调节调节电压调节器(160),可调偏置电流发生器(160)和尺寸可调的逆变器模块(170),电压发生器(100)能够操纵电压产生的速度。

    Method for providing error-resilient digital video content
    34.
    发明公开
    Method for providing error-resilient digital video content 审中-公开
    用于提供错误恢复数字视频内容的方法

    公开(公告)号:EP2582141A2

    公开(公告)日:2013-04-17

    申请号:EP12188339.1

    申请日:2012-10-12

    Abstract: A method for providing error-resilient video content may include receiving video data reflective of multiple video frames; encoding the video data to generate a plurality of packets representing a video frame; transmitting the first group of packets to at least two receivers (110); receiving feedback information regarding receiving status of respective ones of the plurality of packets; examining error indications regarding the at least two receivers (110) based on the feedback information and implementing a first error-correction policy if a variation in the error indications among the at least two receivers (110) is below a first error threshold and a second error-correction policy if the variation is above the first error threshold. At least one of the first and second error-correction policies includes transmitting or retransmitting at least one packet using a coding scheme different from a scheme in encoding the plurality of packets already.

    Abstract translation: 用于提供错误恢复视频内容的方法可以包括:接收反映多个视频帧的视频数据; 编码视频数据以生成表示视频帧的多个分组; 将第一组分组传送到至少两个接收器(110); 接收关于所述多个分组中的相应分组的接收状态的反馈信息; 基于所述反馈信息检查关于所述至少两个接收器(110)的错误指示,并且如果所述至少两个接收器(110)之间的所述错误指示的变化低于第一错误阈值,则执行第一错误校正策略, 纠错策略,如果变化高于第一个错误阈值。 第一纠错策略和第二纠错策略中的至少一个包括使用与已编码多个分组中的方案不同的编码方案来传送或重传至少一个分组。

    Digital phase-locked loops and frequency adjusting methods thereof
    36.
    发明公开
    Digital phase-locked loops and frequency adjusting methods thereof 有权
    Digitale Phasenregelkreise und Frequenzregelungsverfahrendafür

    公开(公告)号:EP2302800A1

    公开(公告)日:2011-03-30

    申请号:EP10003775.3

    申请日:2010-04-08

    Inventor: Chen, Tse-Peng

    CPC classification number: H03L7/085 H03L7/0891 H03L7/18 H03L2207/50

    Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and -I. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

    Abstract translation: 提供具有相位频率检测器(PFD),3态相位频率检测转换器(3态PFD转换器),环路滤波器和数字压控振荡器的数字锁相环。 PFD接收输入频率和参考频率,并且基于输入频率和参考频率之间的相位差输出第一信号和第二信号。 3态PFD转换器根据第一和第二信号输出3态信号,其中3状态信号呈现在1,0和-I中。 环路滤波器仅基于3态信号输出至少一个控制位。 DCO根据控制位调节输出的振荡频率。

    ULTRA-WIDEBAND RADAR TRANSCEIVER AND OPERATING METHOD THEREOF

    公开(公告)号:EP3650883A1

    公开(公告)日:2020-05-13

    申请号:EP19207039.9

    申请日:2019-11-05

    Inventor: CHI, Hsiang-Feng

    Abstract: An ultra-wideband radar transceiver and an operating method thereof are provided. The ultra-wideband radar transceiver includes a receiving module. The receiving module includes an I/Q signal generator, a first sensing circuit and a second sensing circuit. The I/Q signal generator receives M consecutive echo signals and generates M consecutive in-phase signals and M consecutive quadrature-phase signals accordingly, wherein M is an integer greater than 1. The first sensing circuit is coupled to the I/Q signal generator to receive the M consecutive in-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive in-phase signals to generate a first digital data. The second sensing circuit is coupled to the I/Q signal generator to receive the M consecutive quadrature-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive quadrature-phase signals to generate a second digital data.

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