Abstract:
A radar apparatus (1, 1', 1") and a leakage correction method thereof are provided. The radar apparatus (1, 1', 1") includes a transmitter (100, 100') and a receiver (200, 200', 200'-1, 200", 200"-1). The receiver (200, 200', 200'-1, 200", 200"-1) receives transmitting signals (TS) including a sinewave signal (SS1) from the transmitter (100, 100'). The sinewave signal generator (210, 210') of the receiver (200, 200', 200'-1, 200", 200"-1) generates another sinewave signal (SS2) according to the amplitude of the transmitting signals (TS) or received transmitting signals (RTS). The correcting circuit (250) corrects leakage situation (LS) on the received transmitting signals (RTS) according to another sinewave signal (SS2). The phasor of sinewave form corresponding to the leakage situation (LS) relates to the phasor of another sinewave signal (SS2). Accordingly, the performance of receiver (200, 200', 200'-1, 200", 200"-1) may be improved effectively.
Abstract:
A voltage generator (100) includes an oscillator (130), a charge pump (140) having an input and an output, the input of the charge pump (140) being coupled to the output of the oscillator (130), a first resistor (R1) connected to the output of the charge pump (140), a second resistor (R2) connected to the first resistor (R1), a smoothing capacitor (C1) connected to the second resistor (R2), and a shorting element (150) connected in parallel with the second resistor (R2). When the shorting element is turned on, the second resistor (R2) is bypassed. By including an adjustable regulated voltage regulator (160), an adjustable bias current generator (160) and a size-adjustable inverter module (170), the voltage generator (100) is able to manipulate the speed of voltage generation.
Abstract:
A method for providing error-resilient video content may include receiving video data reflective of multiple video frames; encoding the video data to generate a plurality of packets representing a video frame; transmitting the first group of packets to at least two receivers (110); receiving feedback information regarding receiving status of respective ones of the plurality of packets; examining error indications regarding the at least two receivers (110) based on the feedback information and implementing a first error-correction policy if a variation in the error indications among the at least two receivers (110) is below a first error threshold and a second error-correction policy if the variation is above the first error threshold. At least one of the first and second error-correction policies includes transmitting or retransmitting at least one packet using a coding scheme different from a scheme in encoding the plurality of packets already.
Abstract:
A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and -I. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.
Abstract:
An ultra-wideband radar transceiver and an operating method thereof are provided. The ultra-wideband radar transceiver includes a receiving module. The receiving module includes an I/Q signal generator, a first sensing circuit and a second sensing circuit. The I/Q signal generator receives M consecutive echo signals and generates M consecutive in-phase signals and M consecutive quadrature-phase signals accordingly, wherein M is an integer greater than 1. The first sensing circuit is coupled to the I/Q signal generator to receive the M consecutive in-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive in-phase signals to generate a first digital data. The second sensing circuit is coupled to the I/Q signal generator to receive the M consecutive quadrature-phase signals and is configured to perform integration and analog-to-digital conversion on the M consecutive quadrature-phase signals to generate a second digital data.