中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4082 records (took 0.048 seconds)

    Signature cell
    31.
    发明专利
    Signature cell 审中-公开
    签名单元

    公开(公告)号：JP2004304192A

    公开(公告)日：2004-10-28

    申请号：JP2004096529

    申请日：2004-03-29

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： SOUNDRON AGNEL

    IPC: G01R31/317 ,  G11C29/40 ,  H01L21/822 ,  H01L27/04

    CPC classification number: G11C29/40 ,  G11C17/14 ,  G11C2029/0405

    Abstract: PROBLEM TO BE SOLVED: To provide an improved test technique for a read-on memory in an integrated circuit.
    SOLUTION: The test technique comprises a memory cell, a built-in self-testing cell, a comparing cell and a signature cell, and the signature cell contains one set of first conductive paths at a first level and one set of second conductive paths at a second level. The paths at the first level are physically separated from the paths at the second level by an insulative substance and a contact is disposed so as to allow both the paths to be electrically connected with each other. A combination of the first and second conductive paths in the connected condition and the non-connected condition gives the bit condition of a standard signature word, and gives an address data to a memory construct and generates a consequential signature word. The consequential signature word is compared with the standard signature word to generate the status condition in a memory construct-programmed condition. The result of success or failure on the memory construct-programmed condition is expressed by using the status condition.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为集成电路中的读取存储器提供改进的测试技术。 解决方案：测试技术包括存储器单元，内置自检单元，比较单元和签名单元，并且签名单元包含一组第一级的第一导电路径和一组第二级 导电路径处于第二级。 第一级的路径通过绝缘物质在物理上与第二级的路径分离，并且设置接触件以允许两条路径彼此电连接。 在连接状态和非连接状态下的第一和第二导电路径的组合给出了标准签名字的位条件，并且给存储器结构提供地址数据并产生后续签名字。 将结果签名字与标准签名字进行比较，以在存储器构造编程条件下生成状态条件。 通过使用状态条件表示存储器构造编程条件下的成功或失败的结果。 版权所有（C）2005，JPO＆NCIPI

    Fingerprint detector with improved sensing surface layer
    33.
    发明专利
    Fingerprint detector with improved sensing surface layer 审中-公开
    具有改进的感应表面层的指纹检测器

    公开(公告)号：JP2004136090A

    公开(公告)日：2004-05-13

    申请号：JP2003353257

    申请日：2003-10-14

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： HWANG MING ,  WANG FUCHAO ,  DANIEL A THOMAS

    IPC: G01B7/28 ,  A61B5/117 ,  G06K9/00 ,  G06T1/00 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

    CPC classification number: G06K9/00053

    Abstract: PROBLEM TO BE SOLVED: To provide a fingerprint detector improved in durability, and its manufacturing method. SOLUTION: This fingerprint detector having a smooth sensing surface brought into contact with a fingerprint has capacitive sensor plates defining an array of sensor cells below the sensing surface and tungsten ESD protection grid lines surrounding each sensor cell. The sensing surface is defined by an alumina layer with the tungsten grid lines embedded therein. The alumina layer provides the sensing surface with improved scratch resistance. The resulting detector is more sensitive in its capacitive sensing due to the relatively high dielectric constant of the alumina layer. COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供改善耐久性的指纹检测器及其制造方法。 解决方案：具有与指纹接触的平滑感测表面的该指纹检测器具有电容式传感器板，其限定感测表面下方的传感器单元的阵列以及围绕每个传感器单元的钨ESD保护网格线。 感测表面由其中嵌入有钨网格线的氧化铝层限定。 氧化铝层为传感表面提供了改进的耐擦伤性。 由于氧化铝层的相对高的介电常数，所得到的检测器在其电容感测中更敏感。 版权所有（C）2004，JPO

    Code group acquisition procedure for umts-fdd receiver
    35.
    发明专利
    Code group acquisition procedure for umts-fdd receiver 审中-公开
    UMTS-FDD接收机的代码组获取程序

    公开(公告)号：JP2003332946A

    公开(公告)日：2003-11-21

    申请号：JP2003139113

    申请日：2003-05-16

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

    Inventor： DARBEL NICOLAS ,  BELVEZE FABRICE ,  FAUX GREGORY

    IPC: H04B1/707

    CPC classification number: H04B1/70735 ,  H04B1/7083 ,  H04B1/709

    Abstract: PROBLEM TO BE SOLVED: To provide an improved technique for initially acquiring a synchronous code group and frame alignment data, using a UMTS-FDD receiver. SOLUTION: For completing a step 2 process, a different synchronous channel is used. In more detail, a complete synchronous channel correlator is used for a demodulation such that it correlates received signals in known time slots for coupling a primary synchronous code with a plurality of secondary synchronous codes each. The coupled correlation provides a step 2 performance improved in the view of the acquisition time and the signal to noise ratio. COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：使用UMTS-FDD接收机提供用于初始获取同步码组和帧对准数据的改进技术。

    解决方案：为了完成步骤2的处理，使用不同的同步通道。 更详细地，使用完整的同步信道相关器进行解调，使得它将已知时隙中的接收信号相关联，以将主同步码与多个次同步码各自耦合。 耦合相关提供了在采集时间和信噪比方面改进的步骤2性能。 版权所有（C）2004，JPO

    Rearrangement hardware for mass memory command queue
    36.
    发明专利
    Rearrangement hardware for mass memory command queue 审中-公开
    重新安排大众记忆命令队伍的硬件

    公开(公告)号：JP2003076499A

    公开(公告)日：2003-03-14

    申请号：JP2002231742

    申请日：2002-08-08

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

    Inventor： LIN WEN

    IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F13/18 ,  G11B5/55

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0674 ,  G11B5/5547

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for improving command queue rearranging process with the load of processor resource decreased.
    SOLUTION: This invention provides a hardware command queue with a memory device for a mass memory system. Plural entries are demarcated within the memory device, at least several among which are active entries. Among the active entries, at lease several are associated with pending access commands with at least one entry as a head entry associated with the active command in operation. Physical target position is stored in each active entry with the calculated servo distance stored in each active entry. A link list including a pointer for defining execution sequence is stored together with the command queue.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种用于改善处理器资源负载的命令队列重排过程的改进技术。 解决方案：本发明提供了一种具有用于大容量存储器系统的存储器装置的硬件命令队列。 多个条目在存储设备内被划分，其中至少几个是活动条目。 在活动条目中，至少有几个与等待访问命令相关联，其中至少有一个条目作为与正在运行的活动命令相关联的头条目。 物理目标位置存储在每个活动条目中，计算出的伺服距离存储在每个活动条目中。 包括用于定义执行顺序的指针的链接列表与命令队列一起存储。

    Data-storage disk having few or no spin-up wedges, and method for wiring servo wedges onto the disk
    38.
    发明专利
    Data-storage disk having few or no spin-up wedges, and method for wiring servo wedges onto the disk 审中-公开
    数据存储盘有几个或没有旋转楔子，以及将伺服电缆连接到磁盘上的方法

    公开(公告)号：JP2003022624A

    公开(公告)日：2003-01-24

    申请号：JP2002187536

    申请日：2002-06-27

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

    Inventor： OZDEMIR HAKAN

    IPC: G11B5/09 ,  G11B5/596 ,  G11B20/12 ,  G11B21/10

    CPC classification number: G11B5/59633

    Abstract: PROBLEM TO BE SOLVED: To provide an improved data storage medium, particularly a data- storage disk having a few or no spin-up wedges.
    SOLUTION: This data-storage disk has a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge identifies the sector in conjunction with both an initial positioning of a read-write head and a data read and write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供改进的数据存储介质，特别是具有少量或不具有旋转楔形的数据存储盘。 解决方案：该数据存储盘具有用于存储数据的磁盘扇区和位于扇区开头的伺服楔。 伺服楔同时结合读写头的初始定位和数据读写操作来识别扇区。 通过使用伺服楔以在读或写操作期间提供磁盘上升的初始头部位置和头部位置，可以通过减少旋转楔子的数量或完全消除磁盘的数据存储容量来增加磁盘的数据存储容量 。

    System and method for correcting soft error in random access memory device
    39.
    发明专利
    System and method for correcting soft error in random access memory device 审中-公开
    用于校正随机访问存储器件中的软错误的系统和方法

    公开(公告)号：JP2002366444A

    公开(公告)日：2002-12-20

    申请号：JP2002128327

    申请日：2002-04-30

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド

    Inventor： LAURENT DUANE GILES

    IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

    CPC classification number: G06F11/1044

    Abstract: PROBLEM TO BE SOLVED: To provide a technology for reducing a soft error in a dynamic memory device.
    SOLUTION: This memory device is provided with a dual port memory equipped with a first port corresponding to an externally started memory access operation and a second port for dealing with the memory access operation related with an error check and error correcting operation. An error module connected to the second port of the dual port memory performs an error check operation with respect to a word read from the dual port memory. An error controller connected to the error module controls the error module to perform the error check operation with respect to each word successively read from the dual port memory through the second port. The error check operation is performed substantially in parallel with the externally started memory access operation to be performed by using the first port of the dual port memory.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供用于减少动态存储装置中的软错误的技术。 解决方案：该存储装置配备有配备有对应于外部启动的存储器访问操作的第一端口的双端口存储器和用于处理与错误校验和纠错操作相关的存储器访问操作的第二端口。 连接到双端口存储器的第二端口的错误模块相对于从双端口存储器读取的字执行错误检查操作。 连接到错误模块的错误控制器控制错误模块，对通过第二端口从双端口存储器连续读取的每个字执行错误检查操作。 基本上与通过使用双端口存储器的第一端口执行的外部启动的存储器访问操作并行执行错误检查操作。

    Integrated circuit and method for classification of electrical device and short circuit protection
    40.
    发明专利
    Integrated circuit and method for classification of electrical device and short circuit protection 有权
    集成电路和电气设备分类方法及短路保护

    公开(公告)号：JP2008290705A

    公开(公告)日：2008-12-04

    申请号：JP2008048164

    申请日：2008-02-28

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： BURLAK GARY JOSEPH ,  MIROWSKI MARIAN

    IPC: B62D53/08 ,  B60R16/02

    CPC classification number: H02H3/12 ,  Y10T307/549

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit and a method for the classification of electrical devices.
    SOLUTION: An integrated circuit device and a method for classifying electrical devices is disclosed. Reference current responses of a plurality of electrical devices are determined and stored in a memory 208. A real-time current response of a specific electrical device is measured and stored in the memory 208. A processor 204 compares the measured real-time current response of the specific electrical device to the reference current responses of the plurality of electrical devices. The classification of the electrical device is then performed based on the comparison.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于电气设备分类的集成电路和方法。 解决方案：公开了一种用于对电气设备进行分类的集成电路器件和方法。 确定多个电气设备的参考电流响应并将其存储在存储器208中。测量特定电气设备的实时电流响应并将其存储在存储器208中。处理器204将测量的实时电流响应与 所述特定电气设备与所述多个电气设备的参考电流响应相关。 然后根据比较进行电气设备的分类。 版权所有（C）2009，JPO＆INPIT

Patent Agency Ranking