公开(公告)号：WO2007010574A1

公开(公告)日：2007-01-25

申请号：PCT/IT2005/000435

申请日：2005-07-22

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

Inventor： RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

IPC: G01L1/18 ,  G01L9/00 ,  G01L9/06

CPC classification number: G01L1/18 ,  B60T2270/82

Abstract: In an integrated pressure sensor (15) with a high full-scale value, a monolithic body (16) of semiconductor material has a first and a second main surface (16a and 16b), opposite and separated by a substantially uniform distance (w). The monolithic body (16) has a bulk region (17), having a sensitive portion (23) next to the first main surface (16a), upon which pressure (P) acts. A first piezoresistive detection element (18) is integrated in the sensitive portion (23) and has a variable resistance as a function of the pressure (P). The bulk region (17) is a solid and compact region and has a thickness substantially equal to the distance (w).

Abstract translation: 在具有高满量程值的集成压力传感器（15）中，半导体材料的整体（16）具有第一和第二主表面（16a和16b），所述第一和第二主表面相对并分开大致均匀的距离（w） 。 整体式主体（16）具有主体区域（17），其具有靠近第一主表面（16a）的敏感部分（23），压力（P）作用在该区域上。 第一压阻检测元件（18）集成在敏感部分（23）中并且具有作为压力（P）的函数的可变电阻。 本体区域（17）是实心且紧凑的区域，其厚度基本上等于距离（w）。

公开(公告)号：WO2007006505A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006673

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity forming the drain epitaxial layer (20) on the semiconductor substrate (100) , forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step forming second sub-regions (Dl, DIa) of the first type of conductivity by means of a second implant step forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51) , carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成有漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤：至少形成 在所述半导体衬底（100）上形成所述漏极外延层（20）的所述第一导电类型的第一半导体外延层（21），通过第一选择性形成第二导电类型的第一子区域（51） 植入步骤通过形成表面半导体层（23）的第二注入步骤形成第一类型导电性的第二子区域（D1，DIa），其中形成第二导电类型的主体区域（40）与 所述第一子区域（51）进行热扩散处理，使得所述第一子区域（51）形成与所述主体区域（40）电接触的单个电连续列区域（50）。

公开(公告)号：WO2007006502A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006670

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  RONSISVALLE, Cesare ,  ENEA, Vincenzo

Inventor： RONSISVALLE, Cesare ,  ENEA, Vincenzo

IPC: H01L29/78 ,  H01L27/07

CPC classification number: H01L29/7803 ,  H01L27/0259 ,  H01L27/0716 ,  H01L29/7302 ,  H01L29/739 ,  H01L29/7808 ,  H01L29/866

Abstract: A power actuator (20) of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor (2) and a low voltage DMOS transistor (3) connected in cascode configuration between a collector terminal (C) of the bipolar transistor (2) and a source terminal (S) of the DMOS transistor (3) and having respective control terminals (B, G). Advantageously according to the invention, the power actuator (20) further comprises at least a Zener diode (21), inserted between the source terminal (S) of the DMOS transistor (3) and the control terminal (B) of the bipolar transistor (2).

Abstract translation: 描述了发射器切换型的电源致动器（20），功率致动器包括至少一个高压双极晶体管（2）和低电压DMOS晶体管（3），其以共源共栅结构连接在集电极端子（C）之间 双极晶体管（2）和DMOS晶体管（3）的源极端子（S）并具有各自的控制端子（B，G）。 有利地，根据本发明，功率致动器（20）还包括至少一个齐纳二极管（21），其插入在DMOS晶体管（3）的源极端（S）和双极晶体管的控制端（B）之间 2）。

公开(公告)号：WO2006103247A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/061118

申请日：2006-03-28

Applicant: STMICROELECTRONICS S.R.L. ,  PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

Inventor： PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

IPC: H03H9/02

CPC classification number: H03H9/02409 ,  G01C19/5726 ,  G01P15/097 ,  G01P15/125 ,  G01P2015/0814 ,  H03H2009/02496

Abstract: A device for controlling the frequency of resonance of an oscillating micro-electromechanical system includes: a microstructure (2), having a first body (10) and a second body (11) , which is capacitively coupled to the first body (10) and elastically oscillatable with respect thereto at a calibratable frequency of resonance (ω R ) , a relative displacement (ΔY) between the second body (11) and the first body (10) being detectable from outside; and an amplifier (21) coupled to the microstructure (2) for detecting the relative displacement (ΔY) . DC decoupling elements (23) are arranged between the amplifier (21) and the microstructure (2).

Abstract translation: 用于控制振荡微机电系统的共振频率的装置包括：具有电容耦合到第一主体（10）的第一主体（10）和第二主体（11）的微结构（2）和 以可校准的共振频率弹性振荡，第二体（11）和第一体（10）之间的相对位移（ΔY）可从外部检测; 以及耦合到微结构（2）的用于检测相对位移（ΔY）的放大器（21）。 DC去耦元件（23）布置在放大器（21）和微结构（2）之间。

公开(公告)号：WO2005117402A1

公开(公告)日：2005-12-08

申请号：PCT/IT2005/000281

申请日：2005-05-19

Applicant: STMICROELECTRONICS S.R.L. ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

Abstract translation: 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换为模拟信号的数模转换器（DAC）; - 低通滤波器（LOW-PASS），连接在所述转换器的输出端，用于以模拟格式接收所述信号，并提供所述重构模拟信号的输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。

公开(公告)号：WO2005091480A1

公开(公告)日：2005-09-29

申请号：PCT/EP2005/050848

申请日：2005-02-28

Applicant: STMICROELECTRONICS s.r.l. ,  ADRAGNA, Claudio ,  FAGNANI, Mauro ,  MORICONI, Ugo

Inventor： ADRAGNA, Claudio ,  FAGNANI, Mauro ,  MORICONI, Ugo

IPC: H02M1/00

CPC classification number: H02M1/32 ,  H02M1/4225 ,  Y02B70/126

Abstract: There is described a device for the correction of the power factor in forced switching power supplies. The device comprises a converter (20) and a control device (100) coupled with the converter (20) in order to obtain from an alternated mains input voltage (Vin) a regulated voltage (Vout) on the output terminal; the converter (20) comprises a power transistor (M) and said control device (100) comprises an error amplifier (3) having in input on the inverting terminal a signal (Vr) proportional to the regulated voltage (Vout) and on the non-inverting terminal a reference voltage (Vref). The signal (Vr) proportional to the regulated voltage is produced by a first resistance (R1) and a second resistance (R2) coupled in series to which is applied said regulated voltage (Vout); a terminal of the second resistance (R2) is connected with the inverting terminal of the error amplifier (3). The device for the correction of the power factor comprises first means (D50) positioned between the first resistance (RI) and the inverting terminal of the error amplifier (3) and second means (50) suitable for detecting the electrical connection of the first means (D50) with the output terminal of said device for the correction of the power factor and suitable for detecting an output signal (Vr2) of the second resistance (R2). The second means (50) are suitable for supplying a malfunction signal (Fault) of the device for the correction of the power factor when the second means (50) detect electric disconnection of the first means (D50) from said output terminal (Out) or when the output signal (Vr2) of the second resistance (R2) tends to zero.

Abstract translation: 描述了用于在强制开关电源中校正功率因数的装置。 该装置包括与转换器（20）耦合的转换器（20）和控制装置（100），以便从输出端子上的交流电源输入电压（Vin）获得调节电压（Vout）; 所述转换器（20）包括功率晶体管（M），并且所述控制装置（100）包括误差放大器（3），所述误差放大器（3）在反相端子上具有与调节电压（Vout）成比例的信号（Vr） - 反相端子参考电压（Vref）。 与调节电压成比例的信号（Vr）由与所述调节电压（Vout）一起施加的串联耦合的第一电阻（R1）和第二电阻（R2）产生; 第二电阻（R2）的端子与误差放大器（3）的反相端连接。 用于校正功率因数的装置包括位于误差放大器（3）的第一电阻（RI）和反相端之间的第一装置（D50）和第二装置（50），适于检测第一装置 （D50）与所述装置的输出端子进行功率因数的校正，并适于检测第二电阻（R2）的输出信号（Vr2）。 第二装置（50）适用于当第二装置（50）检测到第一装置（D50）从所述输出端子（Out）的电断开时，提供用于校正功率因数的装置的故障信号（Fault） 或者当第二电阻（R2）的输出信号（Vr2）变为零时。

公开(公告)号：WO2005083896A1

公开(公告)日：2005-09-09

申请号：PCT/IB2005/000121

申请日：2005-01-14

Applicant: STMICROELECTRONICS S.R.L. ,  RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

Inventor： RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

IPC: H04B1/707

CPC classification number: H04B1/7083 ,  H04B1/70735 ,  H04B2201/7071

Abstract: In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (e mídamble )of said received signal (r) to an input of a correlation bank (111, 151; 203, 253; 303). There are envisaged the operations of: - sending, in a first time interval, the received signal (r) to said correlation bank (303) for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); - sending, in a second time interval, at least part (e mídamble ) of said received signal (r) to said same correlation bank (303) for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); - sending, in a second time interval, the received signal (r) to said same correlation bank (303) for executing the third operation of correlation of at least part (e midamble ) of said received signal (r) with known midamble codes (mid, MPL, MPS). Preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract translation: 为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作 代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分 所述第一，第二和第三相关操作是通过将所述接收信号（r）的至少一部分（emídamble）发送到相关库（111，...）的输入， 151; 203,253; 303）。 设想了以下操作： - 在第一时间间隔中将接收信号（r）发送到所述相关库（303），以执行所述接收信号（r）与辅同步码（SSC）的相关性的第一操作， ; - 在第二时间间隔中将所述接收信号（r）的至少一部分（emídamble）发送到所述相关相关库（303），用于执行所述接收信号（r）与已知中间码（mid）的相关性的第二操作 ，MPL，MPS）; - 接收信号（r）在第二时间间隔发送到所述相关相关库（303），用于执行所述接收信号（r）的至少部分（emidamble）与已知中间码（中间码）的中间相关的第三操作 ，MPL，MPS）。 优先应用在基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统中。

公开(公告)号：WO2004003883A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006639

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3681 ,  G09G3/3674

Abstract: The present invention describes a system for driving rows of a liquid crystal display comprising at least one module (10) for driving one single row of the liquid crystal display. The module comprises an inverter (T11-T12) operating in a supply path between a first (21) and a second (22) supply line of the system, where the first supply line (21) comprises first means (S1) capable of connecting it to a first (VLCD) or to a second (VA) supply voltage and the second supply line (22) comprises second means (S2) capable of connecting it to a third (VB) or to a fourth (VSS) supply voltage. The inverter (T11-T12) is driven by a logic circuitry (11-12) and sends in output (OUT) a drive signal for one single row of the liquid crystal display.

Abstract translation: 本发明描述了一种用于驱动液晶显示器行的系统，包括用于驱动液晶显示器的一行的至少一个模块（10）。 该模块包括在系统的第一（21）和第二（22）电源线之间的供应路径中工作的逆变器（T11-T12），其中第一供电线（21）包括能够连接的第一装置（S1） 第二电源线（22）包括能够将其连接到第三（VB）或第四（VSS）电源电压的第二装置（S2）。 逆变器（T11-T12）由逻辑电路（11-12）驱动，并向输出（OUT）发送一行液晶显示器的驱动信号。

公开(公告)号：WO2004003882A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006638

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G2330/021

Abstract: The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

Abstract translation: 本发明涉及一种用于驱动液晶显示器列的系统，其包括在第一电源电压（VDD）和第二（VSS）电源电压之间的供电路径中工作的逻辑电路（10），其中第一电源电压为（VDD ）高于第二电源电压（VSS）。 逻辑电路（10）能够从其值等于第一（VDD）或第二（VDD）的输出中的输入第二逻辑信号（CP，CN，CP_N，CN_N）中的第一逻辑信号（LOW_FRAME，WHITE_PIX） VSS）电源电压。 该装置包括耦合到逻辑电路（10）并且在大于第一电源电压（VDD）和第二电源电压（VSS））的第三电源电压（VLCD）之间的供电路径中操作的两个电梯装置（11,12） ; 电梯装置（11,12）能够提高第二逻辑信号（CP，CN，CP_N，CN_N）的值。 该器件还包括共用剃须不同电源路径（VLCD-VA，VB-VSS）并具有输出端（OUT）的第一（T11-T12）和第二（T13-T14）对晶体管; 第一（T11-T12）和第二（T13-T14）晶体管对连接到电梯装置（11,12），以便确定列的驱动信号。 该装置包括在第三（VLCD）和第二电源电压（VSS）之间的供应路径中工作并耦合到两个电梯装置（11,12）的关闭电路（15）。 当两对晶体管（T11-T12）中的另一对晶体管（T11-T12）的一对晶体管（T11-T12-T12）中的另一个晶体管 ，T13-T14）处于工作状态。

公开(公告)号：WO2002086965A1

公开(公告)日：2002-10-31

申请号：PCT/IT2001/000192

申请日：2001-04-19

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMBRANO, Raffaele ,  ARTONI, Cesare ,  CORVASCE, Chiara

Inventor： ZAMBRANO, Raffaele ,  ARTONI, Cesare ,  CORVASCE, Chiara

IPC: H01L21/8246

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: An integrated device having: a first conductive region (6A); a second conductive region (11A); an insulating layer (9) arranged between the first and the second conductive region; at least one through opening (36) extending in said insulating layer (9) between the first and the second conductive region; and a contact structure (10A) formed in the through opening and electrically connecting the first conductive region (6A) and the second conductive region (11B). The contact structure (10A) is formed by a conductive material layer (30) that coats the side surface and the bottom of the through opening (36) and surrounds an empty region (35) which is closed at the top by the second conductive region (11A). The conductive material layer (30) preferably comprises a titanium layer (31) and a titanium-nitride layer (32) arranged on top of one another.

Abstract translation: 一种集成装置，具有：第一导电区域（6A）; 第二导电区域（11A）; 布置在第一和第二导电区域之间的绝缘层（9）; 在所述绝缘层（9）中在所述第一和第二导电区域之间延伸的至少一个通孔（36）; 以及形成在所述通孔中并电连接所述第一导电区域（6A）和所述第二导电区域（11B）的接触结构（10A）。 接触结构（10A）由涂覆贯通孔（36）的侧面和底部的导电性材料层（30）形成，并且包围由第二导电区域在顶部封闭的空区域（35） （11A）。 导电材料层（30）优选地包括彼此顶部布置的钛层（31）和氮化钛层（32）。