고조파 조절 회로를 기반으로 한 출력 정합 회로를 이용한저위상 잡음 전압 제어 발진기
    31.
    发明公开
    고조파 조절 회로를 기반으로 한 출력 정합 회로를 이용한저위상 잡음 전압 제어 발진기 无效
    基于谐波控制电路的输出匹配网络的低相位噪声VCO

    公开(公告)号:KR1020090109006A

    公开(公告)日:2009-10-19

    申请号:KR1020080034385

    申请日:2008-04-14

    Inventor: 서철헌 최재원

    CPC classification number: H03B5/1841 H01P1/20372 H01P7/082 H03B2201/036

    Abstract: PURPOSE: A low phase noise VCO using output matching network based on harmonic control circuit is provided to deliver a main signal without loss after removing the second and third harmonics. CONSTITUTION: A harmonic control circuit is comprised of a double parallel stub to remove harmonics. The phenomenon of short circuit impedance point about the second and third harmonics is compensated. The additional microstrip line is included to prevent the thing overlapped on a layout by a stub. The harmonic control circuit is removed by becoming short circuit impedance about the second and third harmonics.

    Abstract translation: 目的:提供使用基于谐波控制电路的输出匹配网络的低相位噪声VCO,在去除第二和第三谐波之后,无损耗地传送主信号。 构成:谐波控制电路由双平行短路组成,以去除谐波。 关于第二和第三谐波的短路阻抗点的现象得到补偿。 包括附加的微带线,以防止通过存根重叠布局的东西。 通过成为关于第二和第三谐波的短路阻抗去除谐波控制电路。

    수정발진기
    32.
    发明公开
    수정발진기 有权
    水晶单元

    公开(公告)号:KR1020070056199A

    公开(公告)日:2007-06-04

    申请号:KR1020050114522

    申请日:2005-11-29

    Inventor: 이종필

    CPC classification number: H03H9/1021 H03B5/32 H03B2200/002 H03B2201/036

    Abstract: A crystal oscillator is provided to safely mount a crystal piece by forming a cavity of the ceramic package widely. A crystal oscillator includes a ceramic package, an electrode pad(21), a frequency oscillating piezoelectric element(5), a conductive adhesive, a bump(7), and a lid(4). The ceramic package has a plurality of ceramic layers(1,2) to form cavities(20,30). The electrode pad(21) is formed on an upper surface of one of the plurality of ceramic layers(1,2). One end of the frequency oscillating piezoelectric element(5) is fixed on the electrode pad(21). The conductive adhesive is coated on an upper surface of the electrode pad(21) to adhere one end of the piezoelectric element(5). The bump(7) is formed inside the ceramic package. The lid(4) covers an upper part of the ceramic package to seal the ceramic package. The bump(7) is made of tungsten or nickel, and the other end of the piezoelectric element(5) is placed on an upper surface of the bump(7).

    Abstract translation: 提供晶体振荡器以通过广泛地形成陶瓷封装的空腔来安全地安装晶体片。 晶体振荡器包括陶瓷封装,电极焊盘(21),频率振荡压电元件(5),导电粘合剂,凸块(7)和盖子(4)。 陶瓷封装具有多个陶瓷层(1,2)以形成空腔(20,30)。 电极焊盘(21)形成在多个陶瓷层(1,2)之一的上表面上。 频率振荡压电元件(5)的一端固定在电极焊盘(21)上。 导电粘合剂涂覆在电极焊盘(21)的上表面上,以粘附压电元件(5)的一端。 凸起(7)形成在陶瓷封装内。 盖(4)覆盖陶瓷封装的上部以密封陶瓷封装。 凸起(7)由钨或镍制成,压电元件(5)的另一端位于凸块(7)的上表面。

    CMOS負電阻及Q加强方法和設備 CMOS NEGATIVE RESISTANCE/Q ENHANCEMENT METHOD AND APPARATUS
    33.
    发明专利
    CMOS負電阻及Q加强方法和設備 CMOS NEGATIVE RESISTANCE/Q ENHANCEMENT METHOD AND APPARATUS 审中-公开
    CMOS负电阻及Q加强方法和设备 CMOS NEGATIVE RESISTANCE/Q ENHANCEMENT METHOD AND APPARATUS

    公开(公告)号:TW200614664A

    公开(公告)日:2006-05-01

    申请号:TW094124743

    申请日:2005-07-21

    IPC: H03H

    CPC classification number: H03B5/1228 H03B5/1212 H03B5/124 H03B2201/036

    Abstract: 一種用以將關聯於一電子共振器系統之品質因數Q最佳化的設備,其中包含一LC共振器以及一提供一負電阻的最佳化電路。該最佳化電路係電子耦接於該共振器電路,且包含兩個CMOS電晶體組對,該CMOS電晶體組對由pmos&nmos組成,各PMOS電晶體之閘極是透過電容器而與該輸入端交跨耦接至該共振器,以及該NMOS電晶體透過電容器而與該輸入端交跨耦接至該共振器。該最佳化電路可接收至少一個控制電壓,以藉由選擇性地偏壓該PMOS電晶體及NMOS電晶體來改變該負電阻。該最佳化電路也包含一電流源,將一受控制電流提供給該CMOS電晶體組對。該電流源位於一供應電壓與該CMOS電晶體組對之間,或者是位在該CMOS電晶體組對與一接地參考電壓之間。一電流控制電壓可控制流經該CMOS電晶體組對的電流。

    Abstract in simplified Chinese: 一种用以将关联于一电子共振器系统之品质因子Q最优化的设备,其中包含一LC共振器以及一提供一负电阻的最优化电路。该最优化电路系电子耦接于该共振器电路,且包含两个CMOS晶体管组对,该CMOS晶体管组对由pmos&nmos组成,各PMOS晶体管之闸极是透过电容器而与该输入端交跨耦接至该共振器,以及该NMOS晶体管透过电容器而与该输入端交跨耦接至该共振器。该最优化电路可接收至少一个控制电压,以借由选择性地偏压该PMOS晶体管及NMOS晶体管来改变该负电阻。该最优化电路也包含一电流源,将一受控制电流提供给该CMOS晶体管组对。该电流源位于一供应电压与该CMOS晶体管组对之间,或者是位在该CMOS晶体管组对与一接地参考电压之间。一电流控制电压可控制流经该CMOS晶体管组对的电流。

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