公开(公告)号：US09653585B2

公开(公告)日：2017-05-16

申请号：US15177231

申请日：2016-06-08

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L31/0328 ,  H01L21/00 ,  H01L21/337 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US09653579B2

公开(公告)日：2017-05-16

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US09646962B1

公开(公告)日：2017-05-09

申请号：US15285985

申请日：2016-10-05

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/861 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0255 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66121 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/7391 ,  H01L29/87

Abstract: A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer.

公开(公告)号：US09633909B2

公开(公告)日：2017-04-25

申请号：US14942504

申请日：2015-11-16

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  Qing Liu

IPC: H01L21/38 ,  H01L21/22 ,  H01L21/8238 ,  H01L29/45 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

公开(公告)号：US20170103917A1

公开(公告)日：2017-04-13

申请号：US15222261

申请日：2016-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L21/768 ,  H01L29/08 ,  H01L23/535 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US09614542B2

公开(公告)日：2017-04-04

申请号：US14573083

申请日：2014-12-17

Applicant: STMICROELECTRONICS, INC.

Inventor： James L. Worley ,  Milad Alwardi

IPC: H03M1/78 ,  H03M1/68

CPC classification number: H03M1/68

Abstract: A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first and second sub-DACs having first and second LSB banks, and an MSB bank coupled between the first and second LSB banks. The decoder may be configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal. The DAC may include an output network coupled to the first and second sub-DACs and configured to generate an analog output signal related to the digital input signal.

公开(公告)号：US09607901B2

公开(公告)日：2017-03-28

申请号：US14705291

申请日：2015-05-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US09601381B2

公开(公告)日：2017-03-21

申请号：US14097565

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US20170047994A1

公开(公告)日：2017-02-16

申请号：US15230227

申请日：2016-08-05

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov

IPC: H04B10/116 ,  H04B3/54 ,  H04W4/00 ,  H04W4/02 ,  H04L29/08 ,  G06Q30/02

CPC classification number: H04B10/116 ,  G06Q30/0267 ,  H04B3/54 ,  H04L67/303 ,  H04W4/021 ,  H04W4/80

Abstract: A hybrid communications network system uses the propagation limitations of Visible Light Communications (VLC) to define location data for portable VLC devices. The location data can be used with specific location-based profiles to provide location-based services to functional zones. The hybrid communications allow location data and connectivity to be available among other communications technologies on the hybrid network.

Abstract translation: 混合通信网络系统使用可见光通信（VLC）的传播限制来定义便携式VLC设备的位置数据。 位置数据可以与特定的基于位置的配置文件一起使用，以向功能区域提供基于位置的服务。 混合通信允许位置数据和连接在混合网络上的其他通信技术中可用。

公开(公告)号：US20170042003A1

公开(公告)日：2017-02-09

申请号：US15230102

申请日：2016-08-05

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov

IPC: H05B37/02 ,  G05B19/042

CPC classification number: H05B37/0272 ,  G05B19/0428 ,  G05B2219/2642 ,  G05B2219/45103 ,  Y02B20/48

Abstract: An intelligent lighting and sensor system is disclosed that includes a processor, a memory arranged to store program logic software, the program logic software executable by the processor, a light control module in communication with at least one light source in which the operation of the light control module is directed according to the program logic software that is executed by the processor, and a sensor interface in communication with a plurality of sensor devices in which the operation of the sensor interface is directed according to the program logic software that is executed by the processor.

Abstract translation: 公开了一种智能照明和传感器系统，其包括处理器，布置成存储程序逻辑软件的存储器，可由处理器执行的程序逻辑软件，与至少一个光源通信的光控制模块，其中光的操作 根据由处理器执行的程序逻辑软件来引导控制模块，以及与多个传感器装置通信的传感器接口，其中根据由所述传感器接口执行的程序逻辑软件来引导传感器接口的操作 处理器。