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    Manufacturing method for an integrated circuit
    41.
    发明专利
    Manufacturing method for an integrated circuit 有权

    公开(公告)号：JP4846889B2

    公开(公告)日：2011-12-28

    申请号：JP33420599

    申请日：1999-11-25

    Applicant: エスティーマイクロエレクトロニクス エス.アール.エル.STMicroelectronics S.r.l.

    Inventor： マウレッリ アルフォンソ ,  ジュセッペ カッペレッティ パオロ

    IPC: H01L27/115 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

    Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate (1), forming a first gate oxide layer (3) for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate (1), forming a second gate oxide layer (5) for memory cells of the memory device; on the first and second gate oxide layers (3,5), forming from a first polysilicon layer (6) gate electrodes (8,9) for the first transistors, and floating-gate electrodes (7) for the memory cells; forming over the floating-gate electrodes (7) of the memory cells a dielectric layer (18); on third portions of the semiconductor substrate (1), forming a third gate oxide layer (24) for second transistors operating at the low operating voltage; on the dielectric layer (18) and on the third portions of the semiconductor substrate (1), forming from a second polysilicon layer (25) control gate electrodes (29) for the memory cells, and gate electrodes (26,27) for the second transistors; in the first portions of the semiconductor substrate (1), forming source and drain regions (12,13;16,17) for the first transistors; in the second portions of the semiconductor substrate (1), forming source and drain regions (30,31) for the memory cells; in the third portions of the semiconductor substrate (1), forming source and drain regions for the second transistors.

    Device for controlling resonant converter
    43.
    发明专利
    Device for controlling resonant converter 审中-公开
    用于控制谐振转换器的装置

    公开(公告)号：JP2011083186A

    公开(公告)日：2011-04-21

    申请号：JP2010229173

    申请日：2010-10-11

    Applicant: Stmicroelectronics Srl ,  エスティーマイクロエレクトロニクス エス.アール.エル.STMicroelectronics S.r.l.

    Inventor： ADRAGNA CLAUDIO

    IPC: H02M3/28

    CPC classification number: H02M3/3376 ,  H02M1/08 ,  H02M2001/0058 ,  Y02B70/1433 ,  Y02B70/1491

    Abstract: PROBLEM TO BE SOLVED: To provide a switching circuit control device for a resonant converter that has a DC current output. SOLUTION: A half-bridge consisting of a first transistor Q1 and a second transistor Q2 generates a cyclic square wave voltage for driving a resonant circuit 300 for a resonant converter. A control device 100 has a circuit means 101 adapted to control the half-bridge according to a charging or discharging time period of a capacitor Ct and to synchronize the start time Tstart of a discharging or charging time period of the capacitor Ct that crosses a zero value of the signal Vs representing the current Is flowing in the resonant circuit 300; and additional means 102 and 103 adapted to control switching-off of the first transistor Q1 or the second transistor Q2 at the end of the discharging or charging time period of the capacitor Ct. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种具有直流电流输出的谐振转换器的开关电路控制装置。 解决方案：由第一晶体管Q1和第二晶体管Q2组成的半桥产生用于驱动用于谐振转换器的谐振电路300的循环方波电压。 控制装置100具有电路装置101，其适于根据电容器Ct的充电或放电时间段来控制半桥，并且使电容器Ct的放电或充电时间段的开始时间Tstart同步为零 表示在谐振电路300中流过的电流Is的信号Vs的值; 以及适于在电容器Ct的放电或充电时间段结束时控制第一晶体管Q1或第二晶体管Q2的截止的附加装置102和103。 版权所有（C）2011，JPO＆INPIT

    Prediction current control at time of driving load in pulse width modulation mode
    47.
    发明专利
    Prediction current control at time of driving load in pulse width modulation mode 有权
    脉冲宽度调制模式下驱动负载时的预测电流控制

    公开(公告)号：JP2010148349A

    公开(公告)日：2010-07-01

    申请号：JP2009281976

    申请日：2009-12-11

    Applicant: Stmicroelectronics Srl ,  エスティーマイクロエレクトロニクスエス.アール.エルSTMicroelectronics S.r.l.

    Inventor： BAGARELLI FULVIO GIACOMO ,  MARANO VINCENZO

    IPC: H02M3/155

    CPC classification number: H02M3/157 ,  H02M2001/0019 ,  H02M2003/1555

    Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling a load current even when a current ripple significantly varies. SOLUTION: The method includes: (A) a step of setting a threshold value of a comparator in correspondence to a reference current value for a load; (B) a step of measuring a first time interval from an active ON state of an ON phase of a power stage to a point of time when the load current reaches the reference current value; and (C) a step of continuously maintaining the power stage in the ON phase. Step (C) is performed while the power stage is further maintained in the predictive ON state for an additional time interval. The additional time interval is determined based on an average value of the first time interval and a time interval of the active ON state measured during a past PWM (pulse width modulation) cycle. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：即使当电流纹波显着变化时，也提供用于控制负载电流的方法。 该方法包括：（A）与负载的基准电流值对应地设定比较器的阈值的步骤; （B）从功率级的导通相的有效接通状态到负载电流达到基准电流值的时刻的第一时间间隔的步骤; 和（C）在ON阶段连续地保持功率级的步骤。 在功率级进一步保持在预测接通状态下进行另外的时间间隔时，执行步骤（C）。 基于第一时间间隔的平均值和在过去的PWM（脉冲宽度调制）周期期间测量的有效接通状态的时间间隔来确定附加时间间隔。 版权所有（C）2010，JPO＆INPIT

    Flash compatible eeprom
    49.
    发明专利
    Flash compatible eeprom 有权

    公开(公告)号：JP4330057B2

    公开(公告)日：2009-09-09

    申请号：JP2000186781

    申请日：2000-06-21

    Applicant: エスティーマイクロエレクトロニクス エス.アール.エル.STMicroelectronics S.r.l.

    Inventor： カッペレッティ パオロ

    IPC: G11C16/02 ,  G11C11/00 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/16 ,  G11C11/005 ,  G11C16/34

    Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout, both are divided into blocks of cells formed in substrate regions isolated from one another. In said second matrix, the information is organized in pages each one contained in a row of memory cells of one of said block of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of polarity opposite to the single supply voltage of the device is applied during an erasing phase to a single wordline selected by means of said row decoder, to page-erase said information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block. A logical circuit confirms the programmed state of each cell containing a logic zero information of the not erased rows of the block after one or more rows or pages have been erased, applying said first boosted voltage to a wordline at a time and said supply voltage to one or more bitlines at a time for confirming a preexistent programmed state, while keeping to ground voltage the common source of all the cells of the block and the confined isolated region of the substrate.

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