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    DISTRIBUTED AMPLIFIER HAVING TAPERED TRANSCONDUCTANCE ARCHITECTURE
    41.
    发明专利
    DISTRIBUTED AMPLIFIER HAVING TAPERED TRANSCONDUCTANCE ARCHITECTURE 审中-公开

    公开(公告)号：JP2003209448A

    公开(公告)日：2003-07-25

    申请号：JP2002373345

    申请日：2002-12-25

    Applicant: AGERE SYSTEMS INC

    Inventor： FRATTI ROGER A

    IPC: H03F3/68 ,  H03F1/18 ,  H03F1/56

    Abstract: PROBLEM TO BE SOLVED: To provide a distributed amplifier having a tapered transconductance architecture. SOLUTION: The distributed amplifier having an improved transimpedance and/or gain is provided with an input transmission line and an output transmission line, the input transmission line forms the input of the distributed amplifier and has a characteristic impedance associated therewith, and the output transmission line forms the output of the distributed amplifier and has a characteristic impedance associated therewith. COPYRIGHT: (C)2003,JPO

    METHOD AND DEVICE FOR LOCKING AND UNLOCKING OF ADAPTIVE CACHE FRAME
    42.
    发明专利
    METHOD AND DEVICE FOR LOCKING AND UNLOCKING OF ADAPTIVE CACHE FRAME 审中-公开

    公开(公告)号：JP2003186743A

    公开(公告)日：2003-07-04

    申请号：JP2002295543

    申请日：2002-10-09

    Applicant: AGERE SYSTEMS INC

    Inventor： DWYER HARRY ,  FERNANDO JOHN SUSANTHA

    IPC: G06F9/46 ,  G06F12/08 ,  G06F12/12

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for locking and unlocking of an adaptive cache frame. SOLUTION: A frame that has been most accessed of late in a cache memory is possible to be accessed again by a task in the near future. By locking these frames that have been most used at the start of switch or interrupt of a task, the cache performance is improved. The list of frames that have been most used of late is updated as the task is executed, and the list is realized as a list of frame addresses or a flag related to each frame. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks a frame being a potential primary factor of remarkable performance deterioration for a task. The adaptive frame unlocking mechanism monitors the number of times of frame errors that the task makes, and, if the number of times of frame errors exceeds a given threshold, unlocks a given frame. COPYRIGHT: (C)2003,JPO

    Comparator circuits having non-complementary input structure
    45.
    发明专利
    Comparator circuits having non-complementary input structure 审中-公开
    具有非补充输入结构的比较器电路

    公开(公告)号：JP2003069394A

    公开(公告)日：2003-03-07

    申请号：JP2002156595

    申请日：2002-05-30

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： GABARA THADDEUS JOHN

    IPC: H03K5/08 ,  G06F7/02 ,  G11C7/06 ,  H03K5/24

    CPC classification number: G11C7/062 ,  G06F7/026 ,  H03K5/2481

    Abstract: PROBLEM TO BE SOLVED: To provide a comparator with non-complementary input structure in order to improve technical problems such as power consumption, number of transistors and a throughput delay in a conventional comparator circuit with a complementary input structure.
    SOLUTION: The non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. However, after the evaluation, the output attains a full digital value but suffers no defective power consumption. Transistors form a cross coupling random access memory cell and perform a comparison of contents of the two legs during the evaluation.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供具有非互补输入结构的比较器，以便改进具有互补输入结构的常规比较器电路中的技术问题，例如功耗，晶体管数量和吞吐量延迟。 解决方案：非互补比较器包括诸如存储器单元，差分放大器或能够执行评估功能的其他类型的电路的评估元件，以及至少第一和第二输入支路，每个耦合到相应的一个 评估元素的第一和第二节点。 然而，在评估之后，输出达到一个完整的数字值，但没有损耗的功耗。 晶体管形成交叉耦合随机存取存储器单元，并且在评估期间执行两条腿的内容的比较。

    PHOTODETECTOR ASSEMBLY
    46.
    发明专利
    PHOTODETECTOR ASSEMBLY 审中-公开

    公开(公告)号：JP2002131568A

    公开(公告)日：2002-05-09

    申请号：JP2001262680

    申请日：2001-08-31

    Applicant: AGERE SYSTEMS INC

    Inventor： CHANDRASEKHAR SETHUMADHAVAN ,  DENTAI ANDREW GOMPERZ ,  LEVINE BARRY F ,  THOMAS GORDON BECK MASON ,  OLA SOJORANDO

    IPC: H01L31/10 ,  G02B6/12 ,  G02B6/122 ,  G02B6/30 ,  G02B6/42 ,  H01L31/0232

    Abstract: PROBLEM TO BE SOLVED: To provide a high speed photodetector having both excellent optical coupling efficiency and high internal efficiency. SOLUTION: This optical device is provided with a first waveguide 204 having a capability for supporting an optical mode. The optical mode has a first size in the inside of the first waveguide 204. The first waveguide 204 is optically coupled to a second waveguide 207. The second waveguide 207 has a capability for supporting the optical mode and the optical mode has a second size in the inside of the second waveguide 207. The photodetector is optically coupled to the second waveguide 207. As a strong point, the first mode size is larger than the second mode size. The first waveguide 204 is capable of being efficiently coupled to an optical source, for example, an optical fiber. The second waveguide 207 is capable of being efficiently coupled to the detector.

    DEVICE EQUIPPED WITH BIPOLAR SEMICONDUCTOR FILM
    47.
    发明专利
    DEVICE EQUIPPED WITH BIPOLAR SEMICONDUCTOR FILM 失效

    公开(公告)号：JP2002026336A

    公开(公告)日：2002-01-25

    申请号：JP2001108267

    申请日：2001-04-06

    Applicant: AGERE SYSTEMS INC

    Inventor： BAO ZHENAN ,  XIAOCHEN LINDA CHEN

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786 ,  H01L51/05 ,  H01L51/30 ,  H01L51/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which is manufactured by the use of organic material having bipolar charge transfer characteristics. SOLUTION: The active layer of a field-effect transistor is formed of organic semiconductor material having bipolar charge transfer characteristics. The semiconductor material is formed of a bipolar polymer film which is effective for the transfer of holes or electrons, containing polymer that has a conjugate skeleton stare possessed of a functional part capable of promoting the transfer of ionic charge. The conjugate skeleton is selected out of thiophene, pyrrole, benzene, naphthalene, anthracene and anthracene-dione, and the functional part is selected out of (i) a functional group containing calboxylate and sulfonate and (ii) a functional site selected from dissimilar atoms provided with isolated electron pairs, containing sulfur, nitrogen, and oxygen. The field effect mobility of the bipolar polymer film is, at least, as high as 10-3 cm2/Vs when it operates as an N-type or a P-type device.

    Pb-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES
    48.
    发明专利
    Pb-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES 审中-公开
    具有改进机械性能的无铅焊枪

    公开(公告)号：JP2014160822A

    公开(公告)日：2014-09-04

    申请号：JP2014032544

    申请日：2014-02-24

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： MARK BACHMAN ,  JOHN W OSENBACH

    IPC: H01L21/60 ,  B23K35/26 ,  C22C13/00

    CPC classification number: H01L2224/16225 ,  H01L2924/15311

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming Pb-free solder bumps with improved mechanical properties and to provide a semiconductor device using the same.SOLUTION: There is provided a semiconductor substrate having a first contact and an undoped electroplated lead-free solder bump 610 formed on the first contact. There is also provided a device package substrate having a second contact and a doped lead-free solder layer 510 containing dopant on the second contact. The dopant reduces a solidification undercooling temperature of the undoped lead-free solder bump when the dopant is incorporated into the lead-free solder bump. The undoped electroplated lead-free solder bump and the doped lead-free solder layer are melted thereby incorporating the dopant into the undoped lead-free solder to form a doped solder bump 140. The solder bump provides an electrical connection between the first contact and the second contact.

    Abstract translation: 要解决的问题：提供一种形成具有改善的机械性能的无铅焊料凸块的方法，并提供使用其的半导体器件。解决方案：提供了具有第一接触和未掺杂电镀的无铅焊料的半导体衬底 突起610形成在第一接触件上。 还提供了具有第二触点的装置封装基板和在第二触点上含有掺杂剂的掺杂的无铅焊料层510。 当掺杂剂掺入到无铅焊料凸块中时，掺杂剂降低未掺杂的无铅焊料凸块的固化过冷却温度。 未掺杂的电镀无铅焊料凸块和掺杂的无铅焊料层熔化，从而将掺杂剂掺入到未掺杂的无铅焊料中以形成掺杂的焊料凸块140.焊料凸点提供第一接触和 第二次联系

    Critical-path circuit for performance monitoring
    50.
    发明专利
    Critical-path circuit for performance monitoring 有权
    用于性能监测的关键路径电路

    公开(公告)号：JP2014045508A

    公开(公告)日：2014-03-13

    申请号：JP2013228190

    申请日：2013-11-01

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： JAMES D CHLIPALA ,  RICHARD P MARTIN ,  RICHARD MUSCAVAGE ,  SEGAN SCOTT A

    IPC: H03K5/19 ,  H03K5/26

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin.SOLUTION: The monitor circuit comprises two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

    Abstract translation: 要解决的问题：提供一种集成电路，其具有用于监视具有目标定时裕度的关键路径中的定时的监视电路。解决方案：监视器电路包括两个移位寄存器，其中之一包括延迟元件，其将延迟值应用于 接收信号。 两个移位寄存器的输入形成能够接收输入信号的信号输入节点。 监视器电路还具有一个具有输出和至少两个输入的逻辑门，每个输入连接到两个移位寄存器的相应输出之一。 逻辑门的输出指示目标定时裕度是否满足或不满足。

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