公开(公告)号：EP0396562A1

公开(公告)日：1990-11-14

申请号：EP88909762.0

申请日：1988-11-10

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

Inventor： JOOS, Peter, Frans, Adelaide ,  VERBIEST, Willem, Jules, Antoine

IPC: H04J3 ,  H04L12

CPC classification number: H04L12/5602 ,  H04J3/247 ,  H04L2012/5636 ,  H04L2012/5684

Abstract: On utilise l'équipement de mesure (SMC) dans un système de commutation de télécommunications, afin de contrôler si la vitesse des cellules de chacune d'une pluralité de chaînes de cellules individuelles multiplexées dans une même liaison, reste dans les limites sur la base desquelles son multiplexage a été permis. A cet effet, ledit équipement contrôle à la fin de chaque intervalle de mesure (MTI), et pour une pluralité de vitesses de cellules [(MS)/A, (MS/2)/A,...], si les probabilités susceptibles de dépasser ces vitesses de cellules sont dépassées ou non. Si c'est le cas, la vitesse des cellules est limitée par des cellules de dérivation. Ainsi une fonction de répartition de probabilité cumulative complémentaire attendue (par rapport à 1) de la vitesse des cellules est approchée par une fonction en forme de cage d'escalier.

公开(公告)号：EP0340870A3

公开(公告)日：1990-06-13

申请号：EP89201120.6

申请日：1989-05-01

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Vanwelsenaers, Arnoul Octaaf Gabriel

IPC: H03L7/18 ,  H03C3/09

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/1978

Abstract: The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and

公开(公告)号：EP0283079A3

公开(公告)日：1990-05-30

申请号：EP88200411.2

申请日：1988-03-05

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Debuysscher, Pierre Leon

IPC: H04J3/06

CPC classification number: H04J3/0632 ,  H04J3/0658 ,  H04L12/1813

Abstract: Asynchronous time division system including at least one node with a switching network (BSN) to which a plurality of user stations (US1/N) are coupled via transmission links and which is adapted to interconnect user stations. At least one (US4) of these user stations is a clock station providing clock information, and upon the establishment of a connection between a plurality of other user stations (US1/3), with the purpose of exchanging synchronous data, each of these stations establishes a connection with this clock station.

公开(公告)号：EP0357618A1

公开(公告)日：1990-03-14

申请号：EP88902469.0

申请日：1988-03-11

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  Alcatel N.V.

Inventor： DEBUYSSCHER, Pierre, Leon

IPC: H04L12

CPC classification number: H04L49/103 ,  H04L49/505 ,  H04L49/557

Abstract: Système de commutation (SW) pour le transfert de paquets de signaux numériques comportant une partie en-tête contenant des information d'acheminement provenant d'une pluralité de terminaux d'entrée (R1 à R16) vers une pluralité de terminaux de sortie (T1 à T16), la destination du terminal de sortie pour un paquet donné étant choisi selon les informations d'acheminement dudit paquet. Le système comporte une pluralité de mémoires (M1 à M8) dont chacune est divisée en une pluralité de zones de stockage, chacune étant associée à un terminal de sortie respectif, des circuits de répétion (RC1 à RC16) servant à diviser chaque paquet reçu en une pluralité de sous-paquets, des circuits de commande (CC1 à CC8) et des circuits de transmission (TC1 à TC16) afin de reconstituer un paquet à partir de ces sous-paquets. Selon les instructions des circuits de commande qui fonctionnent selon les informations d'acheminement d'un paquet, les sous-paquets faisant partie de ce paquet sont transmis aux mémoires respectives et chargés dans les zones de stockage de celle-ci en fonction du terminal de sortie de destination.

公开(公告)号：EP0340870A2

公开(公告)日：1989-11-08

申请号：EP89201120.6

申请日：1989-05-01

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Vanwelsenaers, Arnoul Octaaf Gabriel

IPC: H03L7/18 ,  H03C3/09

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/1978

Abstract: The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and

Abstract translation: 图1所示的数字调制器。 2在其输出端SO提供一个信号，其频率f1等于应用于其输入CLI的时钟频率f2的乘积，除法器DIV2除以的第二整数P和等于另一整数N之和的因子 分频器DIV3分频，有理数（F min + M）/ P。 由于后者小于单位，所以可以使用众所周知的累加器ACC和单周期去除电路CRC。 对于f2 = 3.25MHz，P = 16，N min = 17，可以获得以下调制的载波频率：其中M = @@@，其中m在0和519之间变化，并且$$

公开(公告)号：EP0322026A3

公开(公告)日：1989-09-27

申请号：EP88202852.5

申请日：1988-12-13

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Verbiest, Willem Jules Antoine

IPC: H04J3/16

CPC classification number: H04J3/247

Abstract: Conditional multiplexer wherein an input bitstream having a variable bitrate is allowed as part of a multiplexed output bitstream of input bitstreams or not depending on the result of an operation performed by processing means (TPR1) and which consists in calculating an estimated output bandwidth (B2) of said output bitstream from the mean values (mi) and variances (vi) of the probability distribution functions of the bitrates of said input bitstreams and in the subsequent comparison of said estimated output bandwidth (B2) with the maximum allowable output bandwidth (B). Further processing means (RPR1) continuously measure the mean and variance parameters and continuously verify if the sources of the bitstreams operate within the assigned bandwidths.

公开(公告)号：EP0322026A2

公开(公告)日：1989-06-28

申请号：EP88202852.5

申请日：1988-12-13

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Verbiest, Willem Jules Antoine

IPC: H04J3/16

CPC classification number: H04J3/247

Abstract: Conditional multiplexer wherein an input bitstream having a variable bitrate is allowed as part of a multiplexed output bitstream of input bitstreams or not depending on the result of an operation performed by processing means (TPR1) and which consists in calculating an estimated output bandwidth (B2) of said output bitstream from the mean values (mi) and variances (vi) of the probability distribution functions of the bitrates of said input bitstreams and in the subsequent comparison of said estimated output bandwidth (B2) with the maximum allowable output bandwidth (B). Further processing means (RPR1) continuously measure the mean and variance parameters and continuously verify if the sources of the bitstreams operate within the assigned bandwidths.

Abstract translation: 条件多路复用器，其中根据由处理装置（TPR1）执行的操作的结果，允许具有可变比特率的输入比特流作为输入比特流的多路复用输出比特流的一部分，并且包括计算估计的输出带宽（B2） 根据所述输入比特流的比特率的概率分布函数的平均值（mi）和方差（vi）以及随后的所述估计输出带宽（B2）与最大允许输出带宽（B）的比较， 。 进一步的处理装置（RPR1）连续地测量平均值和方差参数，并连续验证比特流的源是否在分配的带宽内运行。

公开(公告)号：EP0297639A2

公开(公告)日：1989-01-04

申请号：EP88201128.1

申请日：1988-06-04

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Sevenhans, Joannes Mathilda Josephus ,  Rabaey, Dirk Herman Lutgardis Cornelius

IPC: H03F3/30 ,  H03F1/30 ,  H03F1/32

CPC classification number: H03F3/303 ,  H03F1/308 ,  H03F2200/477

Abstract: Correction arrangement, for an amplifier, with two correction circuits (CS1,PM2,NM3/2,CS2,NM4,PM4/3) each connected in parallel across the output stage (PM1,NM1) of the amplifier provided with an input differential amplifier stage (A1), with two differential amplifiers (A2/3) constituting an intermediate stage and with the output stage constituted by the series connection of a PMOS transistor (PM1) and an NMOS transistor (NM1) the junction point (VOUT) of which is connected to the input stage via a feedback circuit (FC). Each correction circuit is able to measure the DC current (I1;I2) through an output transistor (PM1, NM1), to compare a measuring DC current (I3;I4) derived from this measured DC current with a reference DC current (I5;I6) and to change the DC voltage on the gate of the other output transistor (NM1;PM1) in function of the difference and to thus produce a correcting function on the amplifier through the feedback circuit.

Abstract translation: 具有两个校正电路（CS1，PM2，NM3 / 2，CS2，NM4，PM4 / 3）的放大器的校正装置，每个校正电路在放大器的输出级（PM1，NM1）并联并联，并具有输入差分放大器 （A1），具有构成中间级的两个差分放大器（A2 / 3），并且输出级由PMOS晶体管（PM1）和NMOS晶体管（NM1）的串联连接构成，其中的连接点（VOUT） 经由反馈电路（FC）连接到输入级。 每个校正电路能够通过输出晶体管（PM1，NM1）测量直流电流（I1; I2），以将从该测量的直流电流得到的测量直流电流（I3; I4）与参考直流电流（I5; I6），并根据差值改变另一输出晶体管（NM1; PM1）的栅极上的直流电压，从而通过反馈电路在放大器上产生校正功能。

公开(公告)号：EP0297638A1

公开(公告)日：1989-01-04

申请号：EP88201127.3

申请日：1988-06-04

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： De Ceulaer, Bart Jozef Maria ,  Sallaerts, Daniel

IPC: H03K3/356 ,  H03K5/24 ,  G01R19/165

CPC classification number: H03K3/356104

Abstract: The bistate device has a bistate circuit (FF) which when operated brings its outputs (OUT1/2) substantially on respective ones of two voltages (VDD, VSS) by which it is fed, and control means (C) to prevent the operation of this circuit and to thereby bring these outputs (OUT1/2) on a predetermined voltage (VAG) halfway between these two voltages (VDD, VSS) and to disconnect one (VSS) of these two voltages (VDD, VSS) from the circuit, and to enable the operation of the circuit and to thereby disconnect and connect the predetermined voltage (VAG) and this one voltage respectively.

Abstract translation: 双稳态器件具有双稳态电路（FF），其操作时，其输出（OUT1 / 2）基本上在其被馈送的两个电压（VDD，VSS）中的相应的一个上，以及控制装置（C），以防止 并且由此将这些输出（OUT1 / 2）置于这两个电压（VDD，VSS）之间的预定电压（VAG）上，并且从电路断开这两个电压（VDD，VSS）中的一个（VSS） 并且能够使电路的操作，从而分别断开并连接预定电压（VAG）和该一个电压。

公开(公告)号：EP0197972B1

公开(公告)日：1988-11-30

申请号：EP85904815.9

申请日：1985-09-24

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： VERHAEGHEN, Jacobus, Jan, Leon, Gerard

IPC: B65G61/00 ,  B65G47/90

CPC classification number: B65G47/901 ,  B25J9/023 ,  B25J9/1015 ,  B25J9/104 ,  B65G61/00

Abstract: The element moving device includes a supporting structure (29, 30) movable in the X-direction on guide rods (27, 28) and carrying an axle (40) on which an assembly comprising three gear wheels (41, 42, 43) is freely rotatable. Two wheels (41, 42) are engaged by corresponding conveyor belts (44, 45) extending in the X-direction and able to control the rotation or standstill of the axle. The third wheel (43) is coupled to a carriage (54) movable in the Y-direction by a third conveyor belt (48) and carrying the element to be displaced. Each of the two conveyors (41, 42) is controlled by a pair of stepper motors (10, 16) which allow small and accurate displacements to be realized.