公开(公告)号：US06427821B1

公开(公告)日：2002-08-06

申请号：US09693018

申请日：2000-10-20

Applicant: Dong-Hun Lee

Inventor： Dong-Hun Lee

IPC: F16D1352

CPC classification number: F16D13/683 ,  F16D13/62 ,  F16D25/0638 ,  F16D25/12 ,  F16H63/3026

Abstract: A clutch assembly of an automatic transmission includes a clutch drum having a slanted inner surface at a corner formed by circumferentially bending an circumferential edge of the clutch drum, a plurality of friction members alternately arranged in the clutch drum, a piston for actuating the friction members, the piston contacting the friction members, and a cushion ring having a circumferentially slanted outer surface corresponding to the slanted inner surface of the clutch drum, the cushion ring being installed into the clutch drum so as to contact the slanted outer surface of the cushion ring with the slanted inner surface of the clutch drum.

Abstract translation: 自动变速器的离合器组件包括：离合器鼓，其具有在通过周向地弯曲离合器鼓的周缘形成的拐角处的倾斜内表面;多个摩擦构件，交替地布置在离合器鼓中;活塞，用于致动摩擦构件 所述活塞与所述摩擦构件接触，所述缓冲环具有与所述离合器鼓的倾斜内表面对应的周向倾斜的外表面，所述缓冲环安装在所述离合器鼓中以与所述缓冲环的倾斜外表面接触 与离合器鼓的内表面倾斜。

公开(公告)号：US09780097B2

公开(公告)日：2017-10-03

申请号：US14965316

申请日：2015-12-10

Applicant: Kyo-Wook Lee ,  Dong-Hun Lee ,  Hee-Bum Hong ,  Yong-Rae Cho

Inventor： Kyo-Wook Lee ,  Dong-Hun Lee ,  Hee-Bum Hong ,  Yong-Rae Cho

IPC: H01L27/11 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.

公开(公告)号：US20170143548A1

公开(公告)日：2017-05-25

申请号：US15309924

申请日：2015-01-12

Applicant: Dong Hun LEE

Inventor： Dong Hun LEE

IPC: A61F9/06 ,  A42B3/30 ,  A42B3/24

CPC classification number: A61F9/061 ,  A42B3/0406 ,  A42B3/225 ,  A42B3/24 ,  A42B3/30 ,  A61F9/065

Abstract: The present invention relates to a welding helmet including a wireless auto light shield part and a controlling method thereof. More particularly, the present invention relates to a welding helmet including a wireless auto light shield part capable of improving convenience of a welding operation, protecting eyes of a worker from direct light during welding operation, and preventing frost from being formed on the viewing window by shielding or opening a viewing window through elevation of a shield glass while automatically driving the light shield part in a wireless scheme by operation of a torch switch, and a method of controlling the same.

公开(公告)号：US09536881B2

公开(公告)日：2017-01-03

申请号：US14259912

申请日：2014-04-23

Applicant: Shigenobu Maeda ,  Sung-Bong Kim ,  Chang-Wook Moon ,  Dong-Hun Lee ,  Hyung-Soon Jang ,  Sang-Pil Sim

Inventor： Shigenobu Maeda ,  Sung-Bong Kim ,  Chang-Wook Moon ,  Dong-Hun Lee ,  Hyung-Soon Jang ,  Sang-Pil Sim

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/1108

Abstract: Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.

Abstract translation: 提供半导体器件。 半导体器件包括第一鳍片; 与第一鳍相交的第一栅电极; 第一鳍片上的第一栅电极的相应侧上的第一升高源极和/或漏极; 以及与第一鳍相邻的第一场电介质膜。 第一场介电膜包括在第一翅片的顶表面下方的第一部分和从第一部分突出并且与第一升高源和/或漏极接触的第一鳍片的顶表面突出的第二部分。

公开(公告)号：US20160307802A1

公开(公告)日：2016-10-20

申请号：US15050505

申请日：2016-02-23

Applicant: Dong Hun LEE ,  Sunhom Steve PAAK

Inventor： Dong Hun LEE ,  Sunhom Steve PAAK

IPC: H01L21/8234 ,  H01L21/033 ,  H01L27/105

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/1104

Abstract: A semiconductor device fabrication method includes sequentially forming a hard mask layer and a sacrificial layer on a substrate, forming an upper mandrel which includes first to third upper sub-mandrels on the sacrificial layer, the first to third upper sub-mandrels extending in a first direction and being spaced apart from each other in a second direction, a width of the first upper sub-mandrel being smaller than widths of the second and third upper sub-mandrels, forming first spacers on sidewalls of each of the upper sub-mandrels, removing the upper mandrel, etching the sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of sub-mandrels, forming second spacers on sidewalls of the lower sub-mandrels, removing the lower mandrel, patterning the hard mask layer and the substrate using the second spacers as etching masks to form first to tenth fins which extend alongside each other in the first direction and are spaced apart from each other in the second direction, removing the first, second, fifth and eighth fins, and forming a first gate electrode that intersects the third, fourth, sixth and seventh fins, and a second gate electrode that intersects the sixth, seventh, ninth and tenth fins while not intersecting the third and fourth fins.

Abstract translation: 一种半导体器件的制造方法，包括在基板上依次形成硬掩模层和牺牲层，形成在牺牲层上包括第一至第三上部子心轴的上部心轴，第一至第三上部子心轴以第一 方向并且在第二方向上彼此间隔开，第一上部心轴的宽度小于第二和第三上部心轴的宽度，在每个上部心轴的侧壁上形成第一间隔件， 去除上心轴，使用第一间隔件作为蚀刻掩模蚀刻牺牲层，以形成包括多个子心轴的下心轴，在下子心轴的侧壁上形成第二间隔件，移除下心轴， 掩模层和基板，使用第二间隔件作为蚀刻掩模，以形成在第一方向上彼此并列并且与e间隔开的第一至第十个散热片 ach在第二方向上另一个，去除第一，第二，第五和第八鳍片，并且形成与第三，第四，第六和第六鳍片相交的第一栅电极，以及与第六，第七，第九和第九鳍片相交的第二栅电极 第十个翅片，而不与第三和第四个翅片相交。

公开(公告)号：US09343762B2

公开(公告)日：2016-05-17

申请号：US13153823

申请日：2011-06-06

Applicant: Soon Il Jeon ,  Dae Jong Kim ,  Dong Hun Lee

Inventor： Soon Il Jeon ,  Dae Jong Kim ,  Dong Hun Lee

IPC: H01M8/04

CPC classification number: H01M8/04828 ,  H01M8/04156 ,  H01M8/04253 ,  H01M8/04358 ,  H01M8/0438 ,  H01M8/04395 ,  H01M8/04492 ,  H01M8/04835 ,  H01M8/04843 ,  H01M8/0485 ,  H01M8/04992 ,  Y02E60/50

Abstract: The present invention provides a relative humidity and condensed water estimator for a fuel cell and a method for controlling condensed water drain using the same. Here, the relative humidity and condensed water estimator is utilized in control of the fuel cell system involving control of anode condensed water drain by outputting at least two of signals comprising air-side relative humidity, hydrogen-side relative humidity, air-side instantaneous or cumulative condensed water, hydrogen-side instantaneous or cumulative condensed water, instantaneous and cumulative condensed water of the humidifier, membrane water contents, catalyst layer oxygen partial pressure, catalyst layer hydrogen partial pressure, stack or cell voltage, air-side catalyst layer relative humidity, hydrogen-side catalyst layer relative humidity, oxygen supercharging ratio, hydrogen supercharging ratio, residual water in a stack, and residual water in a humidifier.

Abstract translation: 本发明提供一种用于燃料电池的相对湿度和冷凝水估计器以及使用其的冷凝排水控制方法。 这里，通过输出包括空气侧相对湿度，氢侧相对湿度，空气侧瞬时的信号和至少两个信号的至少两个信号，将相对湿度和冷凝水估计器用于控制燃料电池系统，涉及阳极冷凝水排放的控制 累积冷凝水，氢侧瞬时或累积冷凝水，加湿器瞬时累积冷凝水，膜水含量，催化剂层氧分压，催化剂层氢分压，堆叠或电池电压，空气侧催化剂层相对湿度 ，氢侧催化剂层相对湿度，氧气增压比，氢增压比，堆叠中的残留水和加湿器中的残留水。

公开(公告)号：US09312405B2

公开(公告)日：2016-04-12

申请号：US13560951

申请日：2012-07-27

Applicant: Sung-Chul Lee ,  Doo-Youl Lee ,  Young-Jin Kim ,  Young-Su Kim ,  Young-Soo Kim ,  Dong-Hun Lee

Inventor： Sung-Chul Lee ,  Doo-Youl Lee ,  Young-Jin Kim ,  Young-Su Kim ,  Young-Soo Kim ,  Dong-Hun Lee

IPC: H01L21/00 ,  H01L31/0224 ,  H01L31/068 ,  H01L31/18

CPC classification number: H01L31/065 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

Abstract translation: 一种制造太阳能电池的方法包括在半导体衬底上形成具有第一导电类型的掺杂部分，在半导体衬底上生长氧化物层，在氧化物层中形成多个凹陷部分，在半导体上进一步生长氧化物层 在所述半导体衬底的与所述凹部对应的区域上形成具有第二导电类型的掺杂部分，形成与所述第一导电类型的所述掺杂部分电耦合的第一导电电极，以及在所述半导体衬底上形成第二导电电极 并且电耦合到具有第二导电类型的掺杂部分，其中具有第一和第二导电类型的掺杂部分之间的间隙对应于通过进一步生长氧化物层形成的氧化物层的宽度。

公开(公告)号：US09185316B2

公开(公告)日：2015-11-10

申请号：US13307374

申请日：2011-11-30

Applicant: Jin Min Cheon ,  Dong Hun Lee ,  Young Kyun Jeong ,  Yun Jung Kim ,  Seog Heon Ham ,  Jin Ho Seo ,  Shuichi Shimokawa

Inventor： Jin Min Cheon ,  Dong Hun Lee ,  Young Kyun Jeong ,  Yun Jung Kim ,  Seog Heon Ham ,  Jin Ho Seo ,  Shuichi Shimokawa

IPC: H01J40/14 ,  H01L27/00 ,  H03K17/78 ,  H04N5/361 ,  H04N5/365 ,  H04N5/378

CPC classification number: H04N5/361 ,  H04N5/3653 ,  H04N5/378

Abstract: A data sampler and a photo detecting apparatus compensate a reference signal with offset information measured from a unit pixel, and compare an offset-compensated reference signal with a data signal, thereby minimizing the impact of an offset occurring with an increase of gain in the data sampler.

Abstract translation: 数据采样器和光电检测装置用参考信号补偿从单位像素测得的偏移信息，并将偏移补偿参考信号与数据信号进行比较，从而最小化随着数据增益增加而发生偏移的影响 取样器。

公开(公告)号：US09036969B2

公开(公告)日：2015-05-19

申请号：US13618353

申请日：2012-09-14

Applicant: Oh Kee Kwon ,  Chul-Wook Lee ,  Dong-Hun Lee ,  Young Ahn Leem ,  Young-Tak Han ,  Yongsoon Baek ,  Yun C. Chung

Inventor： Oh Kee Kwon ,  Chul-Wook Lee ,  Dong-Hun Lee ,  Young Ahn Leem ,  Young-Tak Han ,  Yongsoon Baek ,  Yun C. Chung

IPC: G02B6/26 ,  C03B37/022 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/305

Abstract: Provided are a spot size converter and a method of manufacturing the spot size converter. The method includes stacking a lower clad layer, a core layer, and a first upper clad layer on a substrate, tapering the first upper clad layer and the core layer in a first direction on a side of the substrate, forming a waveguide layer on the first upper clad layer and the lower clad layer, and etching the waveguide layer, the first upper clad layer, the core layer, and the lower clad layer such that the waveguide layer is wider than a tapered portion of the core layer on the side of the substrate and has the same width as that of the core layer on another side of the substrate.

Abstract translation: 提供了点尺寸转换器和制造光斑尺寸转换器的方法。 该方法包括在基板上层叠下包层，芯层和第一上包覆层，使第一上包覆层和芯层在衬底侧沿第一方向逐渐变细，在衬底的一侧形成波导层 第一上包覆层和下包层，并且蚀刻波导层，第一上包层，芯层和下包层，使得波导层比芯层的锥形部分宽 并且具有与基板的另一侧上的芯层的宽度相同的宽度。

公开(公告)号：US20150028190A1

公开(公告)日：2015-01-29

申请号：US14335309

申请日：2014-07-18

Applicant: Ji-Hun SHIN ,  Chang-Eun KANG ,  Won-Ho CHOI ,  Dong-Hun LEE

Inventor： Ji-Hun SHIN ,  Chang-Eun KANG ,  Won-Ho CHOI ,  Dong-Hun LEE

IPC: H03M1/00 ,  H04N5/378 ,  H03K3/356 ,  H03K23/00 ,  H03M1/12

CPC classification number: H04N5/378 ,  H03K21/38 ,  H03K23/667 ,  H03M1/123 ,  H03M1/14 ,  H03M1/56 ,  H04N5/3575 ,  H04N5/3696 ,  H04N5/3745 ,  H04N13/243 ,  H04N13/254 ,  H04N13/271 ,  H04N2213/001

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract translation: 计数器电路包括第一计数器和第二计数器。 第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号 信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生 响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。