公开(公告)号：CA1306496C

公开(公告)日：1992-08-18

申请号：CA561778

申请日：1988-03-17

Applicant: PRIME COMPUTER INC

Inventor： ARDINI JOSEPH L JR ,  LEFSKY BRIAN ,  FARR BARBARA J

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317

Abstract: METHOD AND APPARATUS FOR HIGH ACCURACY MEASUREMENT OF VLSI COMPONENTS Methods and apparatus for accurately measuring propagation delay through very high speed VLSI devices with a test instrument having errors comparable to the delays being measured. The VLSI device has a plurality of parallel operational signal paths, each with a very short propagation delay, The VLSI device is fabricated with control circuitry for selectively connecting the parallel operational signal paths in series in a test mode so as to define a test signal path comprising multiple operational signal paths. The test signal path has a relatively long propagation delay which can be measured with acceptable accuracy by the test instrument. The test signal path is defined so that it bypasses clocked circuit elements on the VLSI device. Since the operational signal paths are on the same integrated circuit and have very well correlated operating characteristics, the propagation delay through the test signal path is a good representation of the integrated circuit dynamic operation. When the integrated circuit is not in the test mode, the series connections are disabled and the parallel circuits operate in their normally intended manner. A minimum of circuitry is added to the VLSI device in order to implement the test mode.

公开(公告)号：AU625161B2

公开(公告)日：1992-07-02

申请号：AU6134490

申请日：1990-08-27

Applicant: PRIME COMPUTER INC

Inventor： LEFSKY BRIAN ,  NATUSCH MARY ELLEN

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/08 ,  G06F12/12 ,  G06F12/16 ,  G06F12/00

公开(公告)号：CA1302585C

公开(公告)日：1992-06-02

申请号：CA561779

申请日：1988-03-17

Applicant: PRIME COMPUTER INC

Inventor： LEFSKY BRIAN ,  ARDINI JOSEPH L JR ,  SCHWARTZ MICHAEL

IPC: G06F1/10 ,  G06F9/38

Abstract: A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

公开(公告)号：DE3582962D1

公开(公告)日：1991-07-04

申请号：DE3582962

申请日：1985-02-08

Applicant: PRIME COMPUTER INC

Inventor： RODMAN PAUL K ,  ARDINI JOSEPH L ,  PAPWORTH DAVID B

IPC: G06F15/16 ,  G06F12/00 ,  G06F12/08 ,  G06F12/084 ,  G06F15/177

Abstract: A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

公开(公告)号：DE3480669D1

公开(公告)日：1990-01-11

申请号：DE3480669

申请日：1984-02-10

Applicant: PRIME COMPUTER INC

Inventor： LONG CHARLES COMEY ,  LOUNSBURY DAVID MORGAN ,  CURTIN RICHARD ROY

IPC: G11B5/09 ,  G11B20/14 ,  H04L25/49

Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accomodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns.Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established.The circuitry accomodates clock signal phase changes caused by bit shifting by calculating an expected arrival time for a data transition and varying the width of the timing window depending on whether the data transition is received either prior to or subsequent to the expected arrival time.

公开(公告)号：AT39313T

公开(公告)日：1988-12-15

申请号：AT84300794

申请日：1984-02-08

Applicant: PRIME COMPUTER INC

Inventor： BAHR RICHARD G ,  HOGAN THOMAS C

IPC: H04L29/08 ,  H04L7/04 ,  H04L12/42 ,  H04L11/16

Abstract: A ring communications network has a plurality of terminals coupled together to provide a unidirectional communications ring, each terminal being arranged to receive a first digital signal at a data rate associated with the next upstream terminal in the ring and to transmit a second digital signal at a transmit data rate which may be different from the data rate of the received signal. Each signal comprises data packets interleaved with synchronization packets of elastic length to achieve synchronization around the ring. Thus, each terminal has a synchronizing network (12) containing an electric clock generator (32) having a plurality of outputs each shifted in time by a different multiple of 1/8 times the period of a fixed transmit clock signal generated internally by a transmit clock generator (26). In effect, synchronization is achieved by a shallow discretely adjusted delay (FIFO) buffer and sample point readjustment network. The buffer is read at the fixed transmit data rate and loaded at that same rate until the period of elasticity is detected. Then the sample point is reselected to fall in the middle of a transmit bit window effectively changing the FIFO buffer depth.

公开(公告)号：AU1325288A

公开(公告)日：1988-10-13

申请号：AU1325288

申请日：1988-03-17

Applicant: PRIME COMPUTER INC

Inventor： LEFSKY BRIAN ,  ARDINI JOSEPH L JR ,  SCHWARTS MICHAEL

IPC: G06F1/10 ,  G06F9/38 ,  G06F1/04

公开(公告)号：CA1226959A

公开(公告)日：1987-09-15

申请号：CA473957

申请日：1985-02-08

Applicant: PRIME COMPUTER INC

Inventor： RODMAN PAUL K

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F15/16 ,  G06F15/177

Abstract: A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjuction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents. Each element of the list defines one of those cache storage locations and also identifies the location in the CIT memory of the next element in the list.

公开(公告)号：CA1226956A

公开(公告)日：1987-09-15

申请号：CA473959

申请日：1985-02-08

Applicant: PRIME COMPUTER INC

Inventor： TURNER PRESCOTT K

IPC: G06F9/45 ,  G06F9/44

Abstract: A compiler for generating an assembly language listing of instructions for a programmable data processor from a high level programming language has elements for generating from the high level programming language input, an intermediate representation of the programming language input and for generating from the intermediate representation, an assembly language representation of the high level programming language input. The compiler operates generally in accordance with the Glanville-Graham method which enables the compiler to be used with different machines. The resulting retargetable compiler is improved by employing an up/down parsing method in the code generator portion which removes significant restrictions found when LR parsing is employed. The parsing method allows preprocessing of the prefix grammar representing he input intermediate representation for producing, for use by the code generator parsing element, a state table, an extended state table, and a state transition table.

公开(公告)号：CA1216022A

公开(公告)日：1986-12-30

申请号：CA446875

申请日：1984-02-07

Applicant: PRIME COMPUTER INC

Inventor： NELSON DALE H

IPC: H02M3/28 ,  H02M3/33 ,  H02M3/337 ,  H02M7/155

Abstract: A current spreading circuit which in a preferred embodiment is constructed as a power supply circuit having higher power factor and decreased current crest factor. The circuit preferably comprises an input circuit for receiving an input AC voltage and rectifying this voltage and an output circuit for providing a DC output voltage. A pulsewidth-modulator intercouples between the input and output circuits and includes a portion which is adapted to pass input AC current in pulse-width increments with the pulse-width varying in inverse proportion to the AC voltage. In this manner, when the instantaneous AC voltage is low, the pulse widths are wider and conversely when the voltage is high, the pulse widths are narrower. In one version of the invention, the pulse width modulation is carried out by a programmed variable ratio transformer. In one preferred embodiment of the present invention, the current spreading circuit is of a quasi cosecant type while in another preferred embodiment of the invention, there is a combination of pulse-width-modulation with a typical input filter circuit including an OR circuit at the output to provide the necessary combining.